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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl
    from Rev 45 to Rev 46
    Reverse comparison

Rev 45 → Rev 46

/verilog/versatile_library.v
1299,7 → 1299,7
for (i=0;i<word_size/chunk_size;i=i+1) begin
parity[i] = parity_type;
for (j=0;j<chunk_size;j=j+1) begin
parity[i] = data[i+j] ^ parity[i];
parity[i] = data[i*chunk_size+j] ^ parity[i];
end
end
endmodule
1319,7 → 1319,7
for (i=0;i<word_size/chunk_size;i=i+1) begin
error_flag[i] = parity[i] ^ parity_type;
for (j=0;j<chunk_size;j=j+1) begin
error_flag[i] = data[i+j] ^ error_flag[i];
error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
end
end
assign parity_error = |error_flag;
/verilog/versatile_library_actel.v
513,7 → 513,7
for (i=0;i<word_size/chunk_size;i=i+1) begin
parity[i] = parity_type;
for (j=0;j<chunk_size;j=j+1) begin
parity[i] = data[i+j] ^ parity[i];
parity[i] = data[i*chunk_size+j] ^ parity[i];
end
end
endmodule
530,7 → 530,7
for (i=0;i<word_size/chunk_size;i=i+1) begin
error_flag[i] = parity[i] ^ parity_type;
for (j=0;j<chunk_size;j=j+1) begin
error_flag[i] = data[i+j] ^ error_flag[i];
error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
end
end
assign parity_error = |error_flag;
/verilog/versatile_library_altera.v
621,7 → 621,7
for (i=0;i<word_size/chunk_size;i=i+1) begin
parity[i] = parity_type;
for (j=0;j<chunk_size;j=j+1) begin
parity[i] = data[i+j] ^ parity[i];
parity[i] = data[i*chunk_size+j] ^ parity[i];
end
end
endmodule
638,7 → 638,7
for (i=0;i<word_size/chunk_size;i=i+1) begin
error_flag[i] = parity[i] ^ parity_type;
for (j=0;j<chunk_size;j=j+1) begin
error_flag[i] = data[i+j] ^ error_flag[i];
error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
end
end
assign parity_error = |error_flag;
/verilog/logic.v
178,7 → 178,7
for (i=0;i<word_size/chunk_size;i=i+1) begin
parity[i] = parity_type;
for (j=0;j<chunk_size;j=j+1) begin
parity[i] = data[i+j] ^ parity[i];
parity[i] = data[i*chunk_size+j] ^ parity[i];
end
end
endmodule
198,7 → 198,7
for (i=0;i<word_size/chunk_size;i=i+1) begin
error_flag[i] = parity[i] ^ parity_type;
for (j=0;j<chunk_size;j=j+1) begin
error_flag[i] = data[i+j] ^ error_flag[i];
error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
end
end
assign parity_error = |error_flag;

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