URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl
- from Rev 53 to Rev 54
- ↔ Reverse comparison
Rev 53 → Rev 54
/verilog/versatile_library.v
4680,7 → 4680,7
if (rst) |
wb_ack_o <= 1'b0; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i |
wb_ack_o <= wb_stb_i & wb_cyc_i; |
|
assign wb_stall_o = 1'b0; |
|
/verilog/versatile_library_actel.v
1979,7 → 1979,7
if (rst) |
wb_ack_o <= 1'b0; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i |
wb_ack_o <= wb_stb_i & wb_cyc_i; |
assign wb_stall_o = 1'b0; |
endmodule |
// WB ROM |
/verilog/wb.v
510,7 → 510,7
if (rst) |
wb_ack_o <= 1'b0; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i |
wb_ack_o <= wb_stb_i & wb_cyc_i; |
|
assign wb_stall_o = 1'b0; |
|
/verilog/versatile_library_altera.v
2084,7 → 2084,7
if (rst) |
wb_ack_o <= 1'b0; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i |
wb_ack_o <= wb_stb_i & wb_cyc_i; |
assign wb_stall_o = 1'b0; |
endmodule |
// WB ROM |