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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl
    from Rev 62 to Rev 63
    Reverse comparison

Rev 62 → Rev 63

/verilog/versatile_library.v
4643,7 → 4643,7
endgenerate
 
generate
for (i=0;i<nr_of_ports;i=i+1) begin
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
`define MODULE spr
`BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
`undef MODULE
4700,9 → 4700,7
input [sw-1:0] wb_sel_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
reg [dw-1:0] wb_dat_o;
output wb_ack_o;
reg wb_ack_o;
input wb_clk, wb_rst;
 
wire [sw-1:0] cke;
/verilog/versatile_library_actel.v
1942,7 → 1942,7
end
endgenerate
generate
for (i=0;i<nr_of_ports;i=i+1) begin
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
end
endgenerate
1983,9 → 1983,7
input [sw-1:0] wb_sel_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
reg [dw-1:0] wb_dat_o;
output wb_ack_o;
reg wb_ack_o;
input wb_clk, wb_rst;
wire [sw-1:0] cke;
// local wb slave
/verilog/wb.v
439,7 → 439,7
endgenerate
 
generate
for (i=0;i<nr_of_ports;i=i+1) begin
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
`define MODULE spr
`BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
`undef MODULE
496,9 → 496,7
input [sw-1:0] wb_sel_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
reg [dw-1:0] wb_dat_o;
output wb_ack_o;
reg wb_ack_o;
input wb_clk, wb_rst;
 
wire [sw-1:0] cke;
/verilog/versatile_library_altera.v
2047,7 → 2047,7
end
endgenerate
generate
for (i=0;i<nr_of_ports;i=i+1) begin
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
end
endgenerate
2088,9 → 2088,7
input [sw-1:0] wb_sel_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
reg [dw-1:0] wb_dat_o;
output wb_ack_o;
reg wb_ack_o;
input wb_clk, wb_rst;
wire [sw-1:0] cke;
// local wb slave

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