URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl
- from Rev 71 to Rev 70
- ↔ Reverse comparison
Rev 71 → Rev 70
/verilog/versatile_library.v
4809,7 → 4809,7
input wbs_we_i, wbs_stb_i, wbs_cyc_i; |
output [dw-1:0] wbs_dat_o; |
output wbs_ack_o; |
input wb_clk, wb_rst; |
input wbs_clk, wbs_rst; |
|
wire [sw-1:0] cke; |
|
/verilog/versatile_library_actel.v
2071,7 → 2071,7
input wbs_we_i, wbs_stb_i, wbs_cyc_i; |
output [dw-1:0] wbs_dat_o; |
output wbs_ack_o; |
input wb_clk, wb_rst; |
input wbs_clk, wbs_rst; |
wire [sw-1:0] cke; |
reg wbs_ack_o; |
vl_ram_be # ( |
/verilog/wb.v
601,7 → 601,7
input wbs_we_i, wbs_stb_i, wbs_cyc_i; |
output [dw-1:0] wbs_dat_o; |
output wbs_ack_o; |
input wb_clk, wb_rst; |
input wbs_clk, wbs_rst; |
|
wire [sw-1:0] cke; |
|
/verilog/versatile_library_altera.v
2176,7 → 2176,7
input wbs_we_i, wbs_stb_i, wbs_cyc_i; |
output [dw-1:0] wbs_dat_o; |
output wbs_ack_o; |
input wb_clk, wb_rst; |
input wbs_clk, wbs_rst; |
wire [sw-1:0] cke; |
reg wbs_ack_o; |
vl_ram_be # ( |