URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl
- from Rev 72 to Rev 73
- ↔ Reverse comparison
Rev 72 → Rev 73
/verilog/versatile_library.v
3527,7 → 3527,7
parameter mem_size = 256; |
input [(data_width-1):0] d; |
input [(addr_width-1):0] adr; |
input [(addr_width/4)-1:0] be; |
input [(data_width/8)-1:0] be; |
input we; |
output reg [(data_width-1):0] q; |
input clk; |
/verilog/versatile_library_actel.v
1125,7 → 1125,7
parameter mem_size = 256; |
input [(data_width-1):0] d; |
input [(addr_width-1):0] adr; |
input [(addr_width/4)-1:0] be; |
input [(data_width/8)-1:0] be; |
input we; |
output reg [(data_width-1):0] q; |
input clk; |
/verilog/versatile_library_altera.v
1233,7 → 1233,7
parameter mem_size = 256; |
input [(data_width-1):0] d; |
input [(addr_width-1):0] adr; |
input [(addr_width/4)-1:0] be; |
input [(data_width/8)-1:0] be; |
input we; |
output reg [(data_width-1):0] q; |
input clk; |
/verilog/memories.v
108,7 → 108,7
parameter mem_size = 256; |
input [(data_width-1):0] d; |
input [(addr_width-1):0] adr; |
input [(addr_width/4)-1:0] be; |
input [(data_width/8)-1:0] be; |
input we; |
output reg [(data_width-1):0] q; |
input clk; |