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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path 
    /versatile_library/trunk/rtl
    from Rev 81 to Rev 80
    ↔ Reverse comparison
  •

Rev 81 → Rev 80

/verilog/versatile_library.v
4923,7 → 4923,7
output [31:2] address;
output [3:0] be;
output write;
output read;
output reg read;
output beginbursttransfer;
output [3:0] burstcount;
input readdatavalid;
4943,7 → 4943,6
else
last_cyc <= wbm_cyc_o;
 
/*
always @ (posedge clk or posedge rst)
if (rst)
read <= 1'b0;
4952,9 → 4951,7
read <= 1'b1;
else if (!waitrequest)
read <= 1'b0;
*/
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0;
 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
(wbm_bte_o==2'b10) ? 4'd8 :
4975,7 → 4972,7
counter <= counter - 4'd1;
end
end
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
assign write = wbm_cyc & wbm_stb_o & wbm_we_o & counter!=4'd0;
 
`define MODULE wb3wb3_bridge
`BASE`MODULE wbwb3inst (
/verilog/versatile_library_actel.v
2136,7 → 2136,7
output [31:2] address;
output [3:0] be;
output write;
output read;
output reg read;
output beginbursttransfer;
output [3:0] burstcount;
input readdatavalid;
2153,7 → 2153,6
last_cyc <= 1'b0;
else
last_cyc <= wbm_cyc_o;
/*
always @ (posedge clk or posedge rst)
if (rst)
read <= 1'b0;
2162,8 → 2161,6
read <= 1'b1;
else if (!waitrequest)
read <= 1'b0;
*/
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0;
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
(wbm_bte_o==2'b10) ? 4'd8 :
2183,7 → 2180,7
counter <= counter - 4'd1;
end
end
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
assign write = wbm_cyc & wbm_stb_o & wbm_we_o & counter!=4'd0;
vl_wb3wb3_bridge wbwb3inst (
// wishbone slave side
.wbs_dat_i(wbs_dat_i),
/verilog/wb.v
328,7 → 328,7
output [31:2] address;
output [3:0] be;
output write;
output read;
output reg read;
output beginbursttransfer;
output [3:0] burstcount;
input readdatavalid;
348,7 → 348,6
else
last_cyc <= wbm_cyc_o;
 
/*
always @ (posedge clk or posedge rst)
if (rst)
read <= 1'b0;
357,9 → 356,7
read <= 1'b1;
else if (!waitrequest)
read <= 1'b0;
*/
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0;
 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
(wbm_bte_o==2'b10) ? 4'd8 :
380,7 → 377,7
counter <= counter - 4'd1;
end
end
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
assign write = wbm_cyc & wbm_stb_o & wbm_we_o & counter!=4'd0;
 
`define MODULE wb3wb3_bridge
`BASE`MODULE wbwb3inst (
/verilog/versatile_library_altera.v
2241,7 → 2241,7
output [31:2] address;
output [3:0] be;
output write;
output read;
output reg read;
output beginbursttransfer;
output [3:0] burstcount;
input readdatavalid;
2258,7 → 2258,6
last_cyc <= 1'b0;
else
last_cyc <= wbm_cyc_o;
/*
always @ (posedge clk or posedge rst)
if (rst)
read <= 1'b0;
2267,8 → 2266,6
read <= 1'b1;
else if (!waitrequest)
read <= 1'b0;
*/
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0;
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
(wbm_bte_o==2'b10) ? 4'd8 :
2288,7 → 2285,7
counter <= counter - 4'd1;
end
end
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
assign write = wbm_cyc & wbm_stb_o & wbm_we_o & counter!=4'd0;
vl_wb3wb3_bridge wbwb3inst (
// wishbone slave side
.wbs_dat_i(wbs_dat_i),

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