URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl
- from Rev 86 to Rev 90
- ↔ Reverse comparison
Rev 86 → Rev 90
/verilog/versatile_library.v
3713,7 → 3713,7
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`ifdef RAM_BE |
`define MODULE ram_be |
module `BASE`MODULE ( d, adr, be, we, q, clk); |
module `BASE`MODULE ( d, adr, be, re, we, q, clk); |
`undef MODULE |
|
parameter data_width = 32; |
3722,6 → 3722,7
input [(data_width-1):0] d; |
input [(addr_width-1):0] adr; |
input [(data_width/8)-1:0] be; |
input re; |
input we; |
output reg [(data_width-1):0] q; |
input clk; |
3756,7 → 3757,8
if(be[1]) ram[adr][1] <= d[15:8]; |
if(be[0]) ram[adr][0] <= d[7:0]; |
end |
q <= ram[adr]; |
if (re) |
q <= ram[adr]; |
end |
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`else |
3771,6 → 3773,7
endgenerate |
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always @ (posedge clk) |
if (re) |
q <= ram[adr]; |
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`endif |
3778,7 → 3781,7
// Function to access RAM (for use by Verilator). |
function [31:0] get_mem; |
// verilator public |
input [aw-1:0] addr; |
input [addr_width-1:0] addr; |
get_mem = ram[addr]; |
endfunction // get_mem |
|
3785,8 → 3788,8
// Function to write RAM (for use by Verilator). |
function set_mem; |
// verilator public |
input [aw-1:0] addr; |
input [dw-1:0] data; |
input [addr_width-1:0] addr; |
input [data_width-1:0] data; |
ram[addr] = data; |
endfunction // set_mem |
|
4683,7 → 4686,8
input clk, rst; |
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reg [adr_width-1:0] adr; |
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wire [max_burst_width-1:0] to_adr; |
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generate |
if (max_burst_width==0) begin : inst_0 |
reg ack_o; |
4695,8 → 4699,6
ack_o <= cyc_i & stb_i & !ack_o; |
end else begin |
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wire [max_burst_width-1:0] to_adr; |
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reg [1:0] last_cycle; |
localparam idle = 2'b00; |
localparam cyc = 2'b01; |
4714,7 → 4716,7
assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] : |
(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : |
adr[max_burst_width-1:0]; |
assign ack_o = last_cycle == cyc; |
assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i; |
end |
endgenerate |
|
5465,6 → 5467,7
.d(wbs_dat_i), |
.adr(adr), |
.be(wbs_sel_i), |
.re(wbs_stb_i), |
.we(wbs_we_i & wbs_ack_o), |
.q(wbs_dat_o), |
.clk(wb_clk) |
/verilog/versatile_library_actel.v
1235,7 → 1235,7
q <= ram[adr]; |
end |
endmodule |
module vl_ram_be ( d, adr, be, we, q, clk); |
module vl_ram_be ( d, adr, be, re, we, q, clk); |
parameter data_width = 32; |
parameter addr_width = 6; |
parameter mem_size = 1<<addr_width; |
1242,6 → 1242,7
input [(data_width-1):0] d; |
input [(addr_width-1):0] adr; |
input [(data_width/8)-1:0] be; |
input re; |
input we; |
output reg [(data_width-1):0] q; |
input clk; |
1271,7 → 1272,8
if(be[1]) ram[adr][1] <= d[15:8]; |
if(be[0]) ram[adr][0] <= d[7:0]; |
end |
q <= ram[adr]; |
if (re) |
q <= ram[adr]; |
end |
`else |
assign cke = {data_width/8{we}} & be; |
1283,19 → 1285,20
end |
endgenerate |
always @ (posedge clk) |
if (re) |
q <= ram[adr]; |
`endif |
// Function to access RAM (for use by Verilator). |
function [31:0] get_mem; |
// verilator public |
input [aw-1:0] addr; |
input [addr_width-1:0] addr; |
get_mem = ram[addr]; |
endfunction // get_mem |
// Function to write RAM (for use by Verilator). |
function set_mem; |
// verilator public |
input [aw-1:0] addr; |
input [dw-1:0] data; |
input [addr_width-1:0] addr; |
input [data_width-1:0] data; |
ram[addr] = data; |
endfunction // set_mem |
endmodule |
1958,6 → 1961,7
output ack_o; |
input clk, rst; |
reg [adr_width-1:0] adr; |
wire [max_burst_width-1:0] to_adr; |
generate |
if (max_burst_width==0) begin : inst_0 |
reg ack_o; |
1968,7 → 1972,6
else |
ack_o <= cyc_i & stb_i & !ack_o; |
end else begin |
wire [max_burst_width-1:0] to_adr; |
reg [1:0] last_cycle; |
localparam idle = 2'b00; |
localparam cyc = 2'b01; |
1986,7 → 1989,7
assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] : |
(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : |
adr[max_burst_width-1:0]; |
assign ack_o = last_cycle == cyc; |
assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i; |
end |
endgenerate |
generate |
2585,6 → 2588,7
.d(wbs_dat_i), |
.adr(adr), |
.be(wbs_sel_i), |
.re(wbs_stb_i), |
.we(wbs_we_i & wbs_ack_o), |
.q(wbs_dat_o), |
.clk(wb_clk) |
/verilog/wb.v
57,7 → 57,8
input clk, rst; |
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reg [adr_width-1:0] adr; |
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wire [max_burst_width-1:0] to_adr; |
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generate |
if (max_burst_width==0) begin : inst_0 |
reg ack_o; |
69,8 → 70,6
ack_o <= cyc_i & stb_i & !ack_o; |
end else begin |
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wire [max_burst_width-1:0] to_adr; |
|
reg [1:0] last_cycle; |
localparam idle = 2'b00; |
localparam cyc = 2'b01; |
88,7 → 87,7
assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] : |
(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : |
adr[max_burst_width-1:0]; |
assign ack_o = last_cycle == cyc; |
assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i; |
end |
endgenerate |
|
839,6 → 838,7
.d(wbs_dat_i), |
.adr(adr), |
.be(wbs_sel_i), |
.re(wbs_stb_i), |
.we(wbs_we_i & wbs_ack_o), |
.q(wbs_dat_o), |
.clk(wb_clk) |
/verilog/versatile_library_altera.v
1343,7 → 1343,7
q <= ram[adr]; |
end |
endmodule |
module vl_ram_be ( d, adr, be, we, q, clk); |
module vl_ram_be ( d, adr, be, re, we, q, clk); |
parameter data_width = 32; |
parameter addr_width = 6; |
parameter mem_size = 1<<addr_width; |
1350,6 → 1350,7
input [(data_width-1):0] d; |
input [(addr_width-1):0] adr; |
input [(data_width/8)-1:0] be; |
input re; |
input we; |
output reg [(data_width-1):0] q; |
input clk; |
1379,7 → 1380,8
if(be[1]) ram[adr][1] <= d[15:8]; |
if(be[0]) ram[adr][0] <= d[7:0]; |
end |
q <= ram[adr]; |
if (re) |
q <= ram[adr]; |
end |
`else |
assign cke = {data_width/8{we}} & be; |
1391,19 → 1393,20
end |
endgenerate |
always @ (posedge clk) |
if (re) |
q <= ram[adr]; |
`endif |
// Function to access RAM (for use by Verilator). |
function [31:0] get_mem; |
// verilator public |
input [aw-1:0] addr; |
input [addr_width-1:0] addr; |
get_mem = ram[addr]; |
endfunction // get_mem |
// Function to write RAM (for use by Verilator). |
function set_mem; |
// verilator public |
input [aw-1:0] addr; |
input [dw-1:0] data; |
input [addr_width-1:0] addr; |
input [data_width-1:0] data; |
ram[addr] = data; |
endfunction // set_mem |
endmodule |
2063,6 → 2066,7
output ack_o; |
input clk, rst; |
reg [adr_width-1:0] adr; |
wire [max_burst_width-1:0] to_adr; |
generate |
if (max_burst_width==0) begin : inst_0 |
reg ack_o; |
2073,7 → 2077,6
else |
ack_o <= cyc_i & stb_i & !ack_o; |
end else begin |
wire [max_burst_width-1:0] to_adr; |
reg [1:0] last_cycle; |
localparam idle = 2'b00; |
localparam cyc = 2'b01; |
2091,7 → 2094,7
assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] : |
(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : |
adr[max_burst_width-1:0]; |
assign ack_o = last_cycle == cyc; |
assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i; |
end |
endgenerate |
generate |
2690,6 → 2693,7
.d(wbs_dat_i), |
.adr(adr), |
.be(wbs_sel_i), |
.re(wbs_stb_i), |
.we(wbs_we_i & wbs_ack_o), |
.q(wbs_dat_o), |
.clk(wb_clk) |
/verilog/memories.v
102,7 → 102,7
|
`ifdef RAM_BE |
`define MODULE ram_be |
module `BASE`MODULE ( d, adr, be, we, q, clk); |
module `BASE`MODULE ( d, adr, be, re, we, q, clk); |
`undef MODULE |
|
parameter data_width = 32; |
111,6 → 111,7
input [(data_width-1):0] d; |
input [(addr_width-1):0] adr; |
input [(data_width/8)-1:0] be; |
input re; |
input we; |
output reg [(data_width-1):0] q; |
input clk; |
145,7 → 146,8
if(be[1]) ram[adr][1] <= d[15:8]; |
if(be[0]) ram[adr][0] <= d[7:0]; |
end |
q <= ram[adr]; |
if (re) |
q <= ram[adr]; |
end |
|
//E2_else |
160,6 → 162,7
endgenerate |
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always @ (posedge clk) |
if (re) |
q <= ram[adr]; |
|
//E2_endif |
167,7 → 170,7
// Function to access RAM (for use by Verilator). |
function [31:0] get_mem; |
// verilator public |
input [aw-1:0] addr; |
input [addr_width-1:0] addr; |
get_mem = ram[addr]; |
endfunction // get_mem |
|
174,8 → 177,8
// Function to write RAM (for use by Verilator). |
function set_mem; |
// verilator public |
input [aw-1:0] addr; |
input [dw-1:0] data; |
input [addr_width-1:0] addr; |
input [data_width-1:0] data; |
ram[addr] = data; |
endfunction // set_mem |
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