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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

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    /versatile_library/trunk/rtl
    from Rev 91 to Rev 92
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Rev 91 → Rev 92

/verilog/versatile_library.v
91,12 → 91,12
`endif
`endif
 
`ifdef WB_DPRAM
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`ifdef WB_B3_DPRAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef SPR
`define SPR
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`endif
 
3923,12 → 3923,12
 
`ifdef DPRAM_BE_2R2W
`define MODULE dpram_be_2r2w
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, re_a, we_a, clk_a, d_b, q_b, adr_b, re_b, we_b, clk_b );
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
`undef MODULE
 
parameter a_data_width = 32;
parameter a_addr_width = 8;
parameter b_data_width = 32;
parameter b_data_width = a_data_width;
localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
 
3935,13 → 3935,13
input [(a_data_width-1):0] d_a;
input [(a_addr_width-1):0] adr_a;
input [(a_data_width/8-1):0] be_a;
input re_a;
input we_a;
output reg [(a_data_width-1):0] q_a;
input [(b_data_width-1):0] d_b;
input [(b_addr_width-1):0] adr_b;
input re_b,we_b;
output [(b_data_width-1):0] q_b;
input [(b_data_width/8-1):0] be_b;
input we_b;
output reg [(b_data_width-1):0] q_b;
input clk_a, clk_b;
 
`ifdef SYSTEMVERILOG
3952,8 → 3952,6
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
 
logic [3:0][7:0] ram [0:mem_size-1];
reg [a_addr_width-1:0] rd_adr_a;
reg [b_addr_width-1:0] rd_adr_b;
 
always_ff@(posedge clk_a)
begin
3965,30 → 3963,27
end
end
always@(posedge clk_a or posedge rst)
if (rst)
rd_adr_a <= 0;
else if (re_a)
rd_adr_a <= adr_a;
assign q_a = ram[rd_adr_a];
always@(posedge clk_a)
q_a = ram[adr_a];
always_ff@(posedge clk_b)
if(we_b)
ram[adr_b] <= d_b;
begin
if(we_b) begin
if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
end
end
always@(posedge clk_b or posedge rst)
if (rst)
rd_adr_b <= 0;
else if (re_b)
rd_adr_b <= adr_b;
assign q_b = ram[rd_adr_b];
always@(posedge clk_b)
q_b = ram[adr_b];
 
end
endgenerate
 
`else
// This modules requires SystemVerilog
`endif
endmodule
`endif
4557,11 → 4552,9
reg [adr_width-1:0] adr;
wire [max_burst_width-1:0] to_adr;
reg [max_burst_width-1:0] last_adr;
reg [1:0] last_cycle;
localparam idle = 2'b00;
localparam cyc = 2'b01;
localparam ws = 2'b10;
localparam eoc = 2'b11;
reg last_cycle;
localparam idle_or_eoc = 1'b0;
localparam cyc_or_ws = 1'b1;
 
always @ (posedge clk or posedge rst)
if (rst)
4568,7 → 4561,7
last_adr <= {max_burst_width{1'b0}};
else
if (stb_i)
last_adr <=adr_o;
last_adr <=adr_o[max_burst_width-1:0];
 
generate
if (max_burst_width==0) begin : inst_0
4583,18 → 4576,18
 
always @ (posedge clk or posedge rst)
if (rst)
last_cycle <= idle;
last_cycle <= idle_or_eoc;
else
last_cycle <= (!cyc_i) ? idle :
(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
(cyc_i & !stb_i) ? ws :
cyc;
assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
(cyc_i & !stb_i) ? cyc_or_ws : //ws
cyc_or_ws; // cyc
assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
(!stb_i) ? last_adr :
(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
(last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
adr[max_burst_width-1:0];
assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
end
endgenerate
 
5547,74 → 5540,91
endmodule
`endif
 
`ifdef WB_DPRAM
`define MODULE wb_dpram
`ifdef WB_B3_DPRAM
`define MODULE wb_b3_dpram
module `BASE`MODULE (
`undef MODULE
// wishbone slave side a
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
wbsa_clk, wbsa_rst,
// wishbone slave side a
wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
// wishbone slave side b
wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
wbsb_clk, wbsb_rst);
 
parameter data_width = 32;
parameter addr_width = 8;
parameter data_width_a = 32;
parameter data_width_b = data_width_a;
parameter addr_width_a = 8;
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
parameter max_burst_width_a = 4;
parameter max_burst_width_b = max_burst_width_a;
 
parameter dat_o_mask_a = 1;
parameter dat_o_mask_b = 1;
 
input [31:0] wbsa_dat_i;
input [addr_width-1:2] wbsa_adr_i;
input [data_width_a-1:0] wbsa_dat_i;
input [addr_width_a-1:0] wbsa_adr_i;
input [data_width_a/8-1:0] wbsa_sel_i;
input [2:0] wbsa_cti_i;
input [1:0] wbsa_bte_i;
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
output [31:0] wbsa_dat_o;
output [data_width_a-1:0] wbsa_dat_o;
output wbsa_ack_o;
input wbsa_clk, wbsa_rst;
 
input [31:0] wbsb_dat_i;
input [addr_width-1:2] wbsb_adr_i;
input [data_width_b-1:0] wbsb_dat_i;
input [addr_width_b-1:0] wbsb_adr_i;
input [data_width_b/8-1:0] wbsb_sel_i;
input [2:0] wbsb_cti_i;
input [1:0] wbsb_bte_i;
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
output [31:0] wbsb_dat_o;
output [data_width_b-1:0] wbsb_dat_o;
output wbsb_ack_o;
input wbsb_clk, wbsb_rst;
 
wire wbsa_dat_tmp, wbsb_dat_tmp;
wire [addr_width_a-1:0] adr_a;
wire [addr_width_b-1:0] adr_b;
 
`define MODULE dpram_2r2w
`BASE`MODULE # (
`define MODULE wb_adr_inc
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
.cyc_i(wbsa_cyc_i),
.stb_i(wbsa_stb_i),
.cti_i(wbsa_cti_i),
.bte_i(wbsa_bte_i),
.adr_i(wbsa_adr_i),
.we_i(wbsa_we_i),
.ack_o(wbsa_ack_o),
.adr_o(adr_a),
.clk(wbsa_clk),
.rst(wbsa_rst));
 
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
.cyc_i(wbsb_cyc_i),
.stb_i(wbsb_stb_i),
.cti_i(wbsb_cti_i),
.bte_i(wbsb_bte_i),
.adr_i(wbsb_adr_i),
.we_i(wbsb_we_i),
.ack_o(wbsb_ack_o),
.adr_o(adr_b),
.clk(wbsb_clk),
.rst(wbsb_rst));
`undef MODULE
.data_width(data_width), .addr_width(addr_width) )
dpram0(
 
`define MODULE dpram_be_2r2w
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
`undef MODULE
ram_i (
.d_a(wbsa_dat_i),
.q_a(wbsa_dat_tmp),
.adr_a(wbsa_adr_i),
.we_a(wbsa_we_i),
.q_a(wbsa_dat_o),
.adr_a(adr_a),
.be_a(wbsa_sel_i),
.we_a(wbsa_we_i & wbsa_ack_o),
.clk_a(wbsa_clk),
.d_b(wbsb_dat_i),
.q_b(wbsb_dat_tmp),
.adr_b(wbsb_adr_i),
.we_b(wbsb_we_i),
.q_b(wbsb_dat_o),
.adr_b(adr_b),
.be_b(wbsb_sel_i),
.we_b(wbsb_we_i & wbsb_ack_o),
.clk_b(wbsb_clk) );
 
generate if (dat_o_mask_a==1)
assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
endgenerate
generate if (dat_o_mask_a==0)
assign wbsa_dat_o = wbsa_dat_tmp;
endgenerate
 
generate if (dat_o_mask_b==1)
assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
endgenerate
generate if (dat_o_mask_b==0)
assign wbsb_dat_o = wbsb_dat_tmp;
endgenerate
 
`define MODULE spr
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
`undef MODULE
 
endmodule
`endif
//////////////////////////////////////////////////////////////////////
/verilog/versatile_library_actel.v
1396,22 → 1396,22
ram[adr_b] <= d_b;
end
endmodule
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, re_a, we_a, clk_a, d_b, q_b, adr_b, re_b, we_b, clk_b );
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
parameter a_data_width = 32;
parameter a_addr_width = 8;
parameter b_data_width = 32;
parameter b_data_width = a_data_width;
localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
input [(a_data_width-1):0] d_a;
input [(a_addr_width-1):0] adr_a;
input [(a_data_width/8-1):0] be_a;
input re_a;
input we_a;
output reg [(a_data_width-1):0] q_a;
input [(b_data_width-1):0] d_b;
input [(b_addr_width-1):0] adr_b;
input re_b,we_b;
output [(b_data_width-1):0] q_b;
input [(b_data_width/8-1):0] be_b;
input we_b;
output reg [(b_data_width-1):0] q_b;
input clk_a, clk_b;
`ifdef SYSTEMVERILOG
// use a multi-dimensional packed array
1419,8 → 1419,6
generate
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
logic [3:0][7:0] ram [0:mem_size-1];
reg [a_addr_width-1:0] rd_adr_a;
reg [b_addr_width-1:0] rd_adr_b;
always_ff@(posedge clk_a)
begin
if(we_a) begin
1430,24 → 1428,23
if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
end
end
always@(posedge clk_a or posedge rst)
if (rst)
rd_adr_a <= 0;
else if (re_a)
rd_adr_a <= adr_a;
assign q_a = ram[rd_adr_a];
always@(posedge clk_a)
q_a = ram[adr_a];
always_ff@(posedge clk_b)
if(we_b)
ram[adr_b] <= d_b;
always@(posedge clk_b or posedge rst)
if (rst)
rd_adr_b <= 0;
else if (re_b)
rd_adr_b <= adr_b;
assign q_b = ram[rd_adr_b];
begin
if(we_b) begin
if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
end
end
always@(posedge clk_b)
q_b = ram[adr_b];
end
endgenerate
`else
// This modules requires SystemVerilog
`endif
endmodule
// FIFO
1835,17 → 1832,15
reg [adr_width-1:0] adr;
wire [max_burst_width-1:0] to_adr;
reg [max_burst_width-1:0] last_adr;
reg [1:0] last_cycle;
localparam idle = 2'b00;
localparam cyc = 2'b01;
localparam ws = 2'b10;
localparam eoc = 2'b11;
reg last_cycle;
localparam idle_or_eoc = 1'b0;
localparam cyc_or_ws = 1'b1;
always @ (posedge clk or posedge rst)
if (rst)
last_adr <= {max_burst_width{1'b0}};
else
if (stb_i)
last_adr <=adr_o;
last_adr <=adr_o[max_burst_width-1:0];
generate
if (max_burst_width==0) begin : inst_0
reg ack_o;
1858,18 → 1853,18
end else begin
always @ (posedge clk or posedge rst)
if (rst)
last_cycle <= idle;
last_cycle <= idle_or_eoc;
else
last_cycle <= (!cyc_i) ? idle :
(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
(cyc_i & !stb_i) ? ws :
cyc;
assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
(cyc_i & !stb_i) ? cyc_or_ws : //ws
cyc_or_ws; // cyc
assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
(!stb_i) ? last_adr :
(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
(last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
adr[max_burst_width-1:0];
assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
end
endgenerate
generate
2624,58 → 2619,6
assign wb_dat_o = wb_dat & {32{wb_ack}};
assign wb_ack_o = wb_ack;
endmodule
module vl_wb_dpram (
// wishbone slave side a
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
wbsa_clk, wbsa_rst,
// wishbone slave side a
wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
wbsb_clk, wbsb_rst);
parameter data_width = 32;
parameter addr_width = 8;
parameter dat_o_mask_a = 1;
parameter dat_o_mask_b = 1;
input [31:0] wbsa_dat_i;
input [addr_width-1:2] wbsa_adr_i;
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
output [31:0] wbsa_dat_o;
output wbsa_ack_o;
input wbsa_clk, wbsa_rst;
input [31:0] wbsb_dat_i;
input [addr_width-1:2] wbsb_adr_i;
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
output [31:0] wbsb_dat_o;
output wbsb_ack_o;
input wbsb_clk, wbsb_rst;
wire wbsa_dat_tmp, wbsb_dat_tmp;
vl_dpram_2r2w # (
.data_width(data_width), .addr_width(addr_width) )
dpram0(
.d_a(wbsa_dat_i),
.q_a(wbsa_dat_tmp),
.adr_a(wbsa_adr_i),
.we_a(wbsa_we_i),
.clk_a(wbsa_clk),
.d_b(wbsb_dat_i),
.q_b(wbsb_dat_tmp),
.adr_b(wbsb_adr_i),
.we_b(wbsb_we_i),
.clk_b(wbsb_clk) );
generate if (dat_o_mask_a==1)
assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
endgenerate
generate if (dat_o_mask_a==0)
assign wbsa_dat_o = wbsa_dat_tmp;
endgenerate
generate if (dat_o_mask_b==1)
assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
endgenerate
generate if (dat_o_mask_b==0)
assign wbsb_dat_o = wbsb_dat_tmp;
endgenerate
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Arithmetic functions ////
/verilog/wb.v
59,11 → 59,9
reg [adr_width-1:0] adr;
wire [max_burst_width-1:0] to_adr;
reg [max_burst_width-1:0] last_adr;
reg [1:0] last_cycle;
localparam idle = 2'b00;
localparam cyc = 2'b01;
localparam ws = 2'b10;
localparam eoc = 2'b11;
reg last_cycle;
localparam idle_or_eoc = 1'b0;
localparam cyc_or_ws = 1'b1;
 
always @ (posedge clk or posedge rst)
if (rst)
70,7 → 68,7
last_adr <= {max_burst_width{1'b0}};
else
if (stb_i)
last_adr <=adr_o;
last_adr <=adr_o[max_burst_width-1:0];
 
generate
if (max_burst_width==0) begin : inst_0
85,18 → 83,18
 
always @ (posedge clk or posedge rst)
if (rst)
last_cycle <= idle;
last_cycle <= idle_or_eoc;
else
last_cycle <= (!cyc_i) ? idle :
(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
(cyc_i & !stb_i) ? ws :
cyc;
assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
(cyc_i & !stb_i) ? cyc_or_ws : //ws
cyc_or_ws; // cyc
assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
(!stb_i) ? last_adr :
(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
(last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
adr[max_burst_width-1:0];
assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
end
endgenerate
 
1049,73 → 1047,90
endmodule
`endif
 
`ifdef WB_DPRAM
`define MODULE wb_dpram
`ifdef WB_B3_DPRAM
`define MODULE wb_b3_dpram
module `BASE`MODULE (
`undef MODULE
// wishbone slave side a
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
wbsa_clk, wbsa_rst,
// wishbone slave side a
wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
// wishbone slave side b
wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
wbsb_clk, wbsb_rst);
 
parameter data_width = 32;
parameter addr_width = 8;
parameter data_width_a = 32;
parameter data_width_b = data_width_a;
parameter addr_width_a = 8;
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
parameter max_burst_width_a = 4;
parameter max_burst_width_b = max_burst_width_a;
 
parameter dat_o_mask_a = 1;
parameter dat_o_mask_b = 1;
 
input [31:0] wbsa_dat_i;
input [addr_width-1:2] wbsa_adr_i;
input [data_width_a-1:0] wbsa_dat_i;
input [addr_width_a-1:0] wbsa_adr_i;
input [data_width_a/8-1:0] wbsa_sel_i;
input [2:0] wbsa_cti_i;
input [1:0] wbsa_bte_i;
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
output [31:0] wbsa_dat_o;
output [data_width_a-1:0] wbsa_dat_o;
output wbsa_ack_o;
input wbsa_clk, wbsa_rst;
 
input [31:0] wbsb_dat_i;
input [addr_width-1:2] wbsb_adr_i;
input [data_width_b-1:0] wbsb_dat_i;
input [addr_width_b-1:0] wbsb_adr_i;
input [data_width_b/8-1:0] wbsb_sel_i;
input [2:0] wbsb_cti_i;
input [1:0] wbsb_bte_i;
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
output [31:0] wbsb_dat_o;
output [data_width_b-1:0] wbsb_dat_o;
output wbsb_ack_o;
input wbsb_clk, wbsb_rst;
 
wire wbsa_dat_tmp, wbsb_dat_tmp;
wire [addr_width_a-1:0] adr_a;
wire [addr_width_b-1:0] adr_b;
 
`define MODULE dpram_2r2w
`BASE`MODULE # (
`define MODULE wb_adr_inc
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
.cyc_i(wbsa_cyc_i),
.stb_i(wbsa_stb_i),
.cti_i(wbsa_cti_i),
.bte_i(wbsa_bte_i),
.adr_i(wbsa_adr_i),
.we_i(wbsa_we_i),
.ack_o(wbsa_ack_o),
.adr_o(adr_a),
.clk(wbsa_clk),
.rst(wbsa_rst));
 
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
.cyc_i(wbsb_cyc_i),
.stb_i(wbsb_stb_i),
.cti_i(wbsb_cti_i),
.bte_i(wbsb_bte_i),
.adr_i(wbsb_adr_i),
.we_i(wbsb_we_i),
.ack_o(wbsb_ack_o),
.adr_o(adr_b),
.clk(wbsb_clk),
.rst(wbsb_rst));
`undef MODULE
.data_width(data_width), .addr_width(addr_width) )
dpram0(
 
`define MODULE dpram_be_2r2w
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
`undef MODULE
ram_i (
.d_a(wbsa_dat_i),
.q_a(wbsa_dat_tmp),
.adr_a(wbsa_adr_i),
.we_a(wbsa_we_i),
.q_a(wbsa_dat_o),
.adr_a(adr_a),
.be_a(wbsa_sel_i),
.we_a(wbsa_we_i & wbsa_ack_o),
.clk_a(wbsa_clk),
.d_b(wbsb_dat_i),
.q_b(wbsb_dat_tmp),
.adr_b(wbsb_adr_i),
.we_b(wbsb_we_i),
.q_b(wbsb_dat_o),
.adr_b(adr_b),
.be_b(wbsb_sel_i),
.we_b(wbsb_we_i & wbsb_ack_o),
.clk_b(wbsb_clk) );
 
generate if (dat_o_mask_a==1)
assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
endgenerate
generate if (dat_o_mask_a==0)
assign wbsa_dat_o = wbsa_dat_tmp;
endgenerate
 
generate if (dat_o_mask_b==1)
assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
endgenerate
generate if (dat_o_mask_b==0)
assign wbsb_dat_o = wbsb_dat_tmp;
endgenerate
 
`define MODULE spr
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
`undef MODULE
 
endmodule
`endif
/verilog/versatile_library_altera.v
1503,22 → 1503,22
ram[adr_b] <= d_b;
end
endmodule
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, re_a, we_a, clk_a, d_b, q_b, adr_b, re_b, we_b, clk_b );
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
parameter a_data_width = 32;
parameter a_addr_width = 8;
parameter b_data_width = 32;
parameter b_data_width = a_data_width;
localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
input [(a_data_width-1):0] d_a;
input [(a_addr_width-1):0] adr_a;
input [(a_data_width/8-1):0] be_a;
input re_a;
input we_a;
output reg [(a_data_width-1):0] q_a;
input [(b_data_width-1):0] d_b;
input [(b_addr_width-1):0] adr_b;
input re_b,we_b;
output [(b_data_width-1):0] q_b;
input [(b_data_width/8-1):0] be_b;
input we_b;
output reg [(b_data_width-1):0] q_b;
input clk_a, clk_b;
`ifdef SYSTEMVERILOG
// use a multi-dimensional packed array
1526,8 → 1526,6
generate
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
logic [3:0][7:0] ram [0:mem_size-1];
reg [a_addr_width-1:0] rd_adr_a;
reg [b_addr_width-1:0] rd_adr_b;
always_ff@(posedge clk_a)
begin
if(we_a) begin
1537,24 → 1535,23
if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
end
end
always@(posedge clk_a or posedge rst)
if (rst)
rd_adr_a <= 0;
else if (re_a)
rd_adr_a <= adr_a;
assign q_a = ram[rd_adr_a];
always@(posedge clk_a)
q_a = ram[adr_a];
always_ff@(posedge clk_b)
if(we_b)
ram[adr_b] <= d_b;
always@(posedge clk_b or posedge rst)
if (rst)
rd_adr_b <= 0;
else if (re_b)
rd_adr_b <= adr_b;
assign q_b = ram[rd_adr_b];
begin
if(we_b) begin
if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
end
end
always@(posedge clk_b)
q_b = ram[adr_b];
end
endgenerate
`else
// This modules requires SystemVerilog
`endif
endmodule
// FIFO
1940,17 → 1937,15
reg [adr_width-1:0] adr;
wire [max_burst_width-1:0] to_adr;
reg [max_burst_width-1:0] last_adr;
reg [1:0] last_cycle;
localparam idle = 2'b00;
localparam cyc = 2'b01;
localparam ws = 2'b10;
localparam eoc = 2'b11;
reg last_cycle;
localparam idle_or_eoc = 1'b0;
localparam cyc_or_ws = 1'b1;
always @ (posedge clk or posedge rst)
if (rst)
last_adr <= {max_burst_width{1'b0}};
else
if (stb_i)
last_adr <=adr_o;
last_adr <=adr_o[max_burst_width-1:0];
generate
if (max_burst_width==0) begin : inst_0
reg ack_o;
1963,18 → 1958,18
end else begin
always @ (posedge clk or posedge rst)
if (rst)
last_cycle <= idle;
last_cycle <= idle_or_eoc;
else
last_cycle <= (!cyc_i) ? idle :
(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
(cyc_i & !stb_i) ? ws :
cyc;
assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
(cyc_i & !stb_i) ? cyc_or_ws : //ws
cyc_or_ws; // cyc
assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
(!stb_i) ? last_adr :
(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
(last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
adr[max_burst_width-1:0];
assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
end
endgenerate
generate
2729,58 → 2724,6
assign wb_dat_o = wb_dat & {32{wb_ack}};
assign wb_ack_o = wb_ack;
endmodule
module vl_wb_dpram (
// wishbone slave side a
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
wbsa_clk, wbsa_rst,
// wishbone slave side a
wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
wbsb_clk, wbsb_rst);
parameter data_width = 32;
parameter addr_width = 8;
parameter dat_o_mask_a = 1;
parameter dat_o_mask_b = 1;
input [31:0] wbsa_dat_i;
input [addr_width-1:2] wbsa_adr_i;
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
output [31:0] wbsa_dat_o;
output wbsa_ack_o;
input wbsa_clk, wbsa_rst;
input [31:0] wbsb_dat_i;
input [addr_width-1:2] wbsb_adr_i;
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
output [31:0] wbsb_dat_o;
output wbsb_ack_o;
input wbsb_clk, wbsb_rst;
wire wbsa_dat_tmp, wbsb_dat_tmp;
vl_dpram_2r2w # (
.data_width(data_width), .addr_width(addr_width) )
dpram0(
.d_a(wbsa_dat_i),
.q_a(wbsa_dat_tmp),
.adr_a(wbsa_adr_i),
.we_a(wbsa_we_i),
.clk_a(wbsa_clk),
.d_b(wbsb_dat_i),
.q_b(wbsb_dat_tmp),
.adr_b(wbsb_adr_i),
.we_b(wbsb_we_i),
.clk_b(wbsb_clk) );
generate if (dat_o_mask_a==1)
assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
endgenerate
generate if (dat_o_mask_a==0)
assign wbsa_dat_o = wbsa_dat_tmp;
endgenerate
generate if (dat_o_mask_b==1)
assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
endgenerate
generate if (dat_o_mask_b==0)
assign wbsb_dat_o = wbsb_dat_tmp;
endgenerate
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Arithmetic functions ////
/verilog/defines.v
91,12 → 91,12
`endif
`endif
 
`ifdef WB_DPRAM
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`ifdef WB_B3_DPRAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef SPR
`define SPR
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`endif
 
/verilog/memories.v
312,12 → 312,12
 
`ifdef DPRAM_BE_2R2W
`define MODULE dpram_be_2r2w
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, re_a, we_a, clk_a, d_b, q_b, adr_b, re_b, we_b, clk_b );
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
`undef MODULE
 
parameter a_data_width = 32;
parameter a_addr_width = 8;
parameter b_data_width = 32;
parameter b_data_width = a_data_width;
localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
 
324,13 → 324,13
input [(a_data_width-1):0] d_a;
input [(a_addr_width-1):0] adr_a;
input [(a_data_width/8-1):0] be_a;
input re_a;
input we_a;
output reg [(a_data_width-1):0] q_a;
input [(b_data_width-1):0] d_b;
input [(b_addr_width-1):0] adr_b;
input re_b,we_b;
output [(b_data_width-1):0] q_b;
input [(b_data_width/8-1):0] be_b;
input we_b;
output reg [(b_data_width-1):0] q_b;
input clk_a, clk_b;
 
//E2_ifdef SYSTEMVERILOG
341,8 → 341,6
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
 
logic [3:0][7:0] ram [0:mem_size-1];
reg [a_addr_width-1:0] rd_adr_a;
reg [b_addr_width-1:0] rd_adr_b;
 
always_ff@(posedge clk_a)
begin
354,30 → 352,27
end
end
always@(posedge clk_a or posedge rst)
if (rst)
rd_adr_a <= 0;
else if (re_a)
rd_adr_a <= adr_a;
assign q_a = ram[rd_adr_a];
always@(posedge clk_a)
q_a = ram[adr_a];
always_ff@(posedge clk_b)
if(we_b)
ram[adr_b] <= d_b;
begin
if(we_b) begin
if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
end
end
always@(posedge clk_b or posedge rst)
if (rst)
rd_adr_b <= 0;
else if (re_b)
rd_adr_b <= adr_b;
assign q_b = ram[rd_adr_b];
always@(posedge clk_b)
q_b = ram[adr_b];
 
end
endgenerate
 
//E2_else
// This modules requires SystemVerilog
//E2_endif
endmodule
`endif

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