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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/sim
    from Rev 102 to Rev 136
    Reverse comparison

Rev 102 → Rev 136

/rtl_sim/run/Makefile
1,4 → 1,5
VERILOG_FILES = ./../../../rtl/verilog/versatile_library.v
INC_DIR = ./../../../rtl/verilog
 
tb_wb_b3_ram_be:
vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_B3_RAM_BE $(VERILOG_FILES) > wb_b3_ram_be.v
14,7 → 15,7
vlog -reportprogress 300 -work work ./../../../bench/tb_wb_b3_dpram.v
 
tb_wb_cache:
vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_CACHE +define+WB_RAM +define+RAM_BE $(VERILOG_FILES) > wb_cache.v
vppreproc --noline --noblank +define+SYSTEMVERILOG +incdir+$(INC_DIR) +define+WB_AVALON_MEM_CACHE +define+WB_RAM +define+RAM_BE +define+WB_AVALON_MEM_CACHE $(VERILOG_FILES) > wb_cache.v
vlog -reportprogress 300 -work work ./wb_cache.v
vlog -reportprogress 300 -work work ./../../../bench/wbm.v
vlog -reportprogress 300 -work work ./../../../bench/tb_wb_cache.v

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