URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library/trunk/sim
- from Rev 136 to Rev 102
- ↔ Reverse comparison
Rev 136 → Rev 102
/rtl_sim/run/Makefile
1,5 → 1,4
VERILOG_FILES = ./../../../rtl/verilog/versatile_library.v |
INC_DIR = ./../../../rtl/verilog |
|
tb_wb_b3_ram_be: |
vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_B3_RAM_BE $(VERILOG_FILES) > wb_b3_ram_be.v |
15,7 → 14,7
vlog -reportprogress 300 -work work ./../../../bench/tb_wb_b3_dpram.v |
|
tb_wb_cache: |
vppreproc --noline --noblank +define+SYSTEMVERILOG +incdir+$(INC_DIR) +define+WB_AVALON_MEM_CACHE +define+WB_RAM +define+RAM_BE +define+WB_AVALON_MEM_CACHE $(VERILOG_FILES) > wb_cache.v |
vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_CACHE +define+WB_RAM +define+RAM_BE $(VERILOG_FILES) > wb_cache.v |
vlog -reportprogress 300 -work work ./wb_cache.v |
vlog -reportprogress 300 -work work ./../../../bench/wbm.v |
vlog -reportprogress 300 -work work ./../../../bench/tb_wb_cache.v |