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/rtl/verilog/versatile_library.v
2111,3 → 2111,246
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
 
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile library, wishbone stuff ////
//// ////
//// Description ////
//// Wishbone compliant modules ////
//// ////
//// ////
//// To Do: ////
//// - ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// async wb3 - wb3 bridge
`timescale 1ns/1ns
module wb3wb3_bridge (
// wishbone slave side
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
// wishbone master side
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
 
input [31:0] wbs_dat_i;
input [31:2] wbs_adr_i;
input [3:0] wbs_sel_i;
input [1:0] wbs_bte_i;
input [2:0] wbs_cti_i;
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
output [31:0] wbs_dat_o;
output reg wbs_ack_o;
input wbs_clk, wbs_rst;
 
output [31:0] wbm_dat_o;
output reg [31:2] wbm_adr_o;
output [3:0] wbm_sel_o;
output reg [1:0] wbm_bte_o;
output reg [2:0] wbm_cti_o;
output reg wbm_we_o, wbm_cyc_o;
output wbm_stb_o;
input [31:0] wbm_dat_i;
input wbm_ack_i;
input wbm_clk, wbm_rst;
 
parameter addr_width = 4;
 
// bte
parameter linear = 2'b00;
parameter wrap4 = 2'b01;
parameter wrap8 = 2'b10;
parameter wrap16 = 2'b11;
// cti
parameter classic = 3'b000;
parameter incburst = 3'b010;
parameter endofburst = 3'b111;
 
parameter wbs_adr = 1'b0;
parameter wbs_data = 1'b1;
 
parameter wbm_adr0 = 2'b00;
parameter wbm_adr1 = 2'b01;
parameter wbm_data = 2'b10;
 
reg wbs_we_reg;
reg [1:0] wbs_bte_reg;
reg wbs;
wire wbs_eoc_alert, wbm_eoc_alert;
reg wbs_eoc, wbm_eoc;
reg [1:0] wbm;
 
reg [1:16] wbs_count, wbm_count;
 
reg wbs_ack_o_rd;
wire wbs_ack_o_wr;
 
wire [35:0] a_d, a_q, b_d, b_q;
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
reg a_rd_reg;
wire b_rd_adr, b_rd_data;
reg b_rd_data_reg;
reg [35:0] temp;
 
`define WE 5
`define BTE 4:3
`define CTI 2:0
 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
wbs_eoc <= 1'b0;
else
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
wbs_eoc <= wbs_bte_i==linear;
else if (wbs_eoc_alert & (a_rd | a_wr))
wbs_eoc <= 1'b1;
 
cnt_shreg_ce_clear # ( .length(16))
cnt0 (
.cke(wbs_ack_o),
.clear(wbs_eoc),
.q(wbs_count),
.rst(wbs_rst),
.clk(wbs_clk));
 
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
wbs <= wbs_adr;
else
if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
wbs <= wbs_data;
else if (wbs_eoc & wbs_ack_o)
wbs <= wbs_adr;
 
// wbs FIFO
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
(wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full :
1'b0;
assign a_rd = !a_fifo_empty;
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
a_rd_reg <= 1'b0;
else
a_rd_reg <= a_rd;
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
 
assign wbs_dat_o = a_q[35:4];
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
{wbs_we_reg,wbs_bte_reg} <= {1'b0,2'b00};
else
{wbs_we_reg,wbs_bte_reg} <= {wbs_we_i,wbs_bte_i};
 
// wbm FIFO
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
wbm_eoc <= 1'b0;
else
if (wbm==wbm_adr0 & !b_fifo_empty)
wbm_eoc <= b_q[`BTE] == linear;
else if (wbm_eoc_alert & wbm_ack_i)
wbm_eoc <= 1'b1;
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
wbm <= wbm_adr0;
else
if ((wbm==wbm_adr0 & !b_fifo_empty) |
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
(wbm==wbm_adr1 & !wbm_we_o) |
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
 
assign b_d = {wbm_dat_i,4'b1111};
assign b_wr = !wbm_we_o & wbm_ack_i;
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1'b0;
assign b_rd = b_rd_adr | b_rd_data;
 
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
 
cnt_shreg_ce_clear # ( .length(16))
cnt1 (
.cke(wbm_ack_i),
.clear(wbm_eoc),
.q(wbm_count),
.rst(wbm_rst),
.clk(wbm_clk));
 
assign wbm_cyc_o = wbm==wbm_data;
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
(wbm==wbm_data) ? 1'b1 :
1'b0;
 
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
else begin
if (wbm==wbm_adr0 & !b_fifo_empty)
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
else if (wbm_eoc_alert & wbm_ack_i)
wbm_cti_o <= endofburst;
end
 
//async_fifo_dw_simplex_top
vl_fifo_2r2w_async_simplex
# ( .data_width(36), .addr_width(addr_width))
fifo (
// a side
.a_d(a_d),
.a_wr(a_wr),
.a_fifo_full(a_fifo_full),
.a_q(a_q),
.a_rd(a_rd),
.a_fifo_empty(a_fifo_empty),
.a_clk(wbs_clk),
.a_rst(wbs_rst),
// b side
.b_d(b_d),
.b_wr(b_wr),
.b_fifo_full(b_fifo_full),
.b_q(b_q),
.b_rd(b_rd),
.b_fifo_empty(b_fifo_empty),
.b_clk(wbm_clk),
.b_rst(wbm_rst)
);
endmodule
/rtl/verilog/versatile_library_actel.v
1683,3 → 1683,215
# (.addr_width(addr_width))
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile library, wishbone stuff ////
//// ////
//// Description ////
//// Wishbone compliant modules ////
//// ////
//// ////
//// To Do: ////
//// - ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// async wb3 - wb3 bridge
`timescale 1ns/1ns
module wb3wb3_bridge (
// wishbone slave side
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
// wishbone master side
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
input [31:0] wbs_dat_i;
input [31:2] wbs_adr_i;
input [3:0] wbs_sel_i;
input [1:0] wbs_bte_i;
input [2:0] wbs_cti_i;
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
output [31:0] wbs_dat_o;
output reg wbs_ack_o;
input wbs_clk, wbs_rst;
output [31:0] wbm_dat_o;
output reg [31:2] wbm_adr_o;
output [3:0] wbm_sel_o;
output reg [1:0] wbm_bte_o;
output reg [2:0] wbm_cti_o;
output reg wbm_we_o, wbm_cyc_o;
output wbm_stb_o;
input [31:0] wbm_dat_i;
input wbm_ack_i;
input wbm_clk, wbm_rst;
parameter addr_width = 4;
// bte
parameter linear = 2'b00;
parameter wrap4 = 2'b01;
parameter wrap8 = 2'b10;
parameter wrap16 = 2'b11;
// cti
parameter classic = 3'b000;
parameter incburst = 3'b010;
parameter endofburst = 3'b111;
parameter wbs_adr = 1'b0;
parameter wbs_data = 1'b1;
parameter wbm_adr0 = 2'b00;
parameter wbm_adr1 = 2'b01;
parameter wbm_data = 2'b10;
reg wbs_we_reg;
reg [1:0] wbs_bte_reg;
reg wbs;
wire wbs_eoc_alert, wbm_eoc_alert;
reg wbs_eoc, wbm_eoc;
reg [1:0] wbm;
reg [1:16] wbs_count, wbm_count;
reg wbs_ack_o_rd;
wire wbs_ack_o_wr;
wire [35:0] a_d, a_q, b_d, b_q;
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
reg a_rd_reg;
wire b_rd_adr, b_rd_data;
reg b_rd_data_reg;
reg [35:0] temp;
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
wbs_eoc <= 1'b0;
else
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
wbs_eoc <= wbs_bte_i==linear;
else if (wbs_eoc_alert & (a_rd | a_wr))
wbs_eoc <= 1'b1;
cnt_shreg_ce_clear # ( .length(16))
cnt0 (
.cke(wbs_ack_o),
.clear(wbs_eoc),
.q(wbs_count),
.rst(wbs_rst),
.clk(wbs_clk));
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
wbs <= wbs_adr;
else
if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
wbs <= wbs_data;
else if (wbs_eoc & wbs_ack_o)
wbs <= wbs_adr;
// wbs FIFO
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
(wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full :
1'b0;
assign a_rd = !a_fifo_empty;
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
a_rd_reg <= 1'b0;
else
a_rd_reg <= a_rd;
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
assign wbs_dat_o = a_q[35:4];
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
{wbs_we_reg,wbs_bte_reg} <= {1'b0,2'b00};
else
{wbs_we_reg,wbs_bte_reg} <= {wbs_we_i,wbs_bte_i};
// wbm FIFO
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
wbm_eoc <= 1'b0;
else
if (wbm==wbm_adr0 & !b_fifo_empty)
wbm_eoc <= b_q[4:3] == linear;
else if (wbm_eoc_alert & wbm_ack_i)
wbm_eoc <= 1'b1;
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
wbm <= wbm_adr0;
else
if ((wbm==wbm_adr0 & !b_fifo_empty) |
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
(wbm==wbm_adr1 & !wbm_we_o) |
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
assign b_d = {wbm_dat_i,4'b1111};
assign b_wr = !wbm_we_o & wbm_ack_i;
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1'b0;
assign b_rd = b_rd_adr | b_rd_data;
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
cnt_shreg_ce_clear # ( .length(16))
cnt1 (
.cke(wbm_ack_i),
.clear(wbm_eoc),
.q(wbm_count),
.rst(wbm_rst),
.clk(wbm_clk));
assign wbm_cyc_o = wbm==wbm_data;
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
(wbm==wbm_data) ? 1'b1 :
1'b0;
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
else begin
if (wbm==wbm_adr0 & !b_fifo_empty)
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
else if (wbm_eoc_alert & wbm_ack_i)
wbm_cti_o <= endofburst;
end
//async_fifo_dw_simplex_top
vl_fifo_2r2w_async_simplex
# ( .data_width(36), .addr_width(addr_width))
fifo (
// a side
.a_d(a_d),
.a_wr(a_wr),
.a_fifo_full(a_fifo_full),
.a_q(a_q),
.a_rd(a_rd),
.a_fifo_empty(a_fifo_empty),
.a_clk(wbs_clk),
.a_rst(wbs_rst),
// b side
.b_d(b_d),
.b_wr(b_wr),
.b_fifo_full(b_fifo_full),
.b_q(b_q),
.b_rd(b_rd),
.b_fifo_empty(b_fifo_empty),
.b_clk(wbm_clk),
.b_rst(wbm_rst)
);
endmodule
/rtl/verilog/wb.v
0,0 → 1,243
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile library, wishbone stuff ////
//// ////
//// Description ////
//// Wishbone compliant modules ////
//// ////
//// ////
//// To Do: ////
//// - ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// async wb3 - wb3 bridge
`timescale 1ns/1ns
module wb3wb3_bridge (
// wishbone slave side
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
// wishbone master side
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
 
input [31:0] wbs_dat_i;
input [31:2] wbs_adr_i;
input [3:0] wbs_sel_i;
input [1:0] wbs_bte_i;
input [2:0] wbs_cti_i;
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
output [31:0] wbs_dat_o;
output reg wbs_ack_o;
input wbs_clk, wbs_rst;
 
output [31:0] wbm_dat_o;
output reg [31:2] wbm_adr_o;
output [3:0] wbm_sel_o;
output reg [1:0] wbm_bte_o;
output reg [2:0] wbm_cti_o;
output reg wbm_we_o, wbm_cyc_o;
output wbm_stb_o;
input [31:0] wbm_dat_i;
input wbm_ack_i;
input wbm_clk, wbm_rst;
 
parameter addr_width = 4;
 
// bte
parameter linear = 2'b00;
parameter wrap4 = 2'b01;
parameter wrap8 = 2'b10;
parameter wrap16 = 2'b11;
// cti
parameter classic = 3'b000;
parameter incburst = 3'b010;
parameter endofburst = 3'b111;
 
parameter wbs_adr = 1'b0;
parameter wbs_data = 1'b1;
 
parameter wbm_adr0 = 2'b00;
parameter wbm_adr1 = 2'b01;
parameter wbm_data = 2'b10;
 
reg wbs_we_reg;
reg [1:0] wbs_bte_reg;
reg wbs;
wire wbs_eoc_alert, wbm_eoc_alert;
reg wbs_eoc, wbm_eoc;
reg [1:0] wbm;
 
reg [1:16] wbs_count, wbm_count;
 
reg wbs_ack_o_rd;
wire wbs_ack_o_wr;
 
wire [35:0] a_d, a_q, b_d, b_q;
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
reg a_rd_reg;
wire b_rd_adr, b_rd_data;
reg b_rd_data_reg;
reg [35:0] temp;
 
`define WE 5
`define BTE 4:3
`define CTI 2:0
 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
wbs_eoc <= 1'b0;
else
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
wbs_eoc <= wbs_bte_i==linear;
else if (wbs_eoc_alert & (a_rd | a_wr))
wbs_eoc <= 1'b1;
 
cnt_shreg_ce_clear # ( .length(16))
cnt0 (
.cke(wbs_ack_o),
.clear(wbs_eoc),
.q(wbs_count),
.rst(wbs_rst),
.clk(wbs_clk));
 
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
wbs <= wbs_adr;
else
if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
wbs <= wbs_data;
else if (wbs_eoc & wbs_ack_o)
wbs <= wbs_adr;
 
// wbs FIFO
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
(wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full :
1'b0;
assign a_rd = !a_fifo_empty;
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
a_rd_reg <= 1'b0;
else
a_rd_reg <= a_rd;
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
 
assign wbs_dat_o = a_q[35:4];
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
{wbs_we_reg,wbs_bte_reg} <= {1'b0,2'b00};
else
{wbs_we_reg,wbs_bte_reg} <= {wbs_we_i,wbs_bte_i};
 
// wbm FIFO
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
wbm_eoc <= 1'b0;
else
if (wbm==wbm_adr0 & !b_fifo_empty)
wbm_eoc <= b_q[`BTE] == linear;
else if (wbm_eoc_alert & wbm_ack_i)
wbm_eoc <= 1'b1;
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
wbm <= wbm_adr0;
else
if ((wbm==wbm_adr0 & !b_fifo_empty) |
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
(wbm==wbm_adr1 & !wbm_we_o) |
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
 
assign b_d = {wbm_dat_i,4'b1111};
assign b_wr = !wbm_we_o & wbm_ack_i;
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1'b0;
assign b_rd = b_rd_adr | b_rd_data;
 
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
 
cnt_shreg_ce_clear # ( .length(16))
cnt1 (
.cke(wbm_ack_i),
.clear(wbm_eoc),
.q(wbm_count),
.rst(wbm_rst),
.clk(wbm_clk));
 
assign wbm_cyc_o = wbm==wbm_data;
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
(wbm==wbm_data) ? 1'b1 :
1'b0;
 
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
else begin
if (wbm==wbm_adr0 & !b_fifo_empty)
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
else if (wbm_eoc_alert & wbm_ack_i)
wbm_cti_o <= endofburst;
end
 
//async_fifo_dw_simplex_top
vl_fifo_2r2w_async_simplex
# ( .data_width(36), .addr_width(addr_width))
fifo (
// a side
.a_d(a_d),
.a_wr(a_wr),
.a_fifo_full(a_fifo_full),
.a_q(a_q),
.a_rd(a_rd),
.a_fifo_empty(a_fifo_empty),
.a_clk(wbs_clk),
.a_rst(wbs_rst),
// b side
.b_d(b_d),
.b_wr(b_wr),
.b_fifo_full(b_fifo_full),
.b_q(b_q),
.b_rd(b_rd),
.b_fifo_empty(b_fifo_empty),
.b_clk(wbm_clk),
.b_rst(wbm_rst)
);
endmodule
/rtl/verilog/Makefile
15,6 → 15,7
VERILOG_FILES += $(VERILOG_FILES_CNT)
VERILOG_FILES += counters.v
VERILOG_FILES += memories.v
VERILOG_FILES += wb.v
 
VERSATILE_LIBRARIES = versatile_library.v
VERSATILE_LIBRARIES += versatile_library_actel.v
/rtl/verilog/versatile_library_altera.v
1669,3 → 1669,215
# (.addr_width(addr_width))
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile library, wishbone stuff ////
//// ////
//// Description ////
//// Wishbone compliant modules ////
//// ////
//// ////
//// To Do: ////
//// - ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// async wb3 - wb3 bridge
`timescale 1ns/1ns
module wb3wb3_bridge (
// wishbone slave side
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
// wishbone master side
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
input [31:0] wbs_dat_i;
input [31:2] wbs_adr_i;
input [3:0] wbs_sel_i;
input [1:0] wbs_bte_i;
input [2:0] wbs_cti_i;
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
output [31:0] wbs_dat_o;
output reg wbs_ack_o;
input wbs_clk, wbs_rst;
output [31:0] wbm_dat_o;
output reg [31:2] wbm_adr_o;
output [3:0] wbm_sel_o;
output reg [1:0] wbm_bte_o;
output reg [2:0] wbm_cti_o;
output reg wbm_we_o, wbm_cyc_o;
output wbm_stb_o;
input [31:0] wbm_dat_i;
input wbm_ack_i;
input wbm_clk, wbm_rst;
parameter addr_width = 4;
// bte
parameter linear = 2'b00;
parameter wrap4 = 2'b01;
parameter wrap8 = 2'b10;
parameter wrap16 = 2'b11;
// cti
parameter classic = 3'b000;
parameter incburst = 3'b010;
parameter endofburst = 3'b111;
parameter wbs_adr = 1'b0;
parameter wbs_data = 1'b1;
parameter wbm_adr0 = 2'b00;
parameter wbm_adr1 = 2'b01;
parameter wbm_data = 2'b10;
reg wbs_we_reg;
reg [1:0] wbs_bte_reg;
reg wbs;
wire wbs_eoc_alert, wbm_eoc_alert;
reg wbs_eoc, wbm_eoc;
reg [1:0] wbm;
reg [1:16] wbs_count, wbm_count;
reg wbs_ack_o_rd;
wire wbs_ack_o_wr;
wire [35:0] a_d, a_q, b_d, b_q;
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
reg a_rd_reg;
wire b_rd_adr, b_rd_data;
reg b_rd_data_reg;
reg [35:0] temp;
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
wbs_eoc <= 1'b0;
else
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
wbs_eoc <= wbs_bte_i==linear;
else if (wbs_eoc_alert & (a_rd | a_wr))
wbs_eoc <= 1'b1;
cnt_shreg_ce_clear # ( .length(16))
cnt0 (
.cke(wbs_ack_o),
.clear(wbs_eoc),
.q(wbs_count),
.rst(wbs_rst),
.clk(wbs_clk));
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
wbs <= wbs_adr;
else
if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
wbs <= wbs_data;
else if (wbs_eoc & wbs_ack_o)
wbs <= wbs_adr;
// wbs FIFO
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
(wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full :
1'b0;
assign a_rd = !a_fifo_empty;
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
a_rd_reg <= 1'b0;
else
a_rd_reg <= a_rd;
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
assign wbs_dat_o = a_q[35:4];
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
{wbs_we_reg,wbs_bte_reg} <= {1'b0,2'b00};
else
{wbs_we_reg,wbs_bte_reg} <= {wbs_we_i,wbs_bte_i};
// wbm FIFO
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
wbm_eoc <= 1'b0;
else
if (wbm==wbm_adr0 & !b_fifo_empty)
wbm_eoc <= b_q[4:3] == linear;
else if (wbm_eoc_alert & wbm_ack_i)
wbm_eoc <= 1'b1;
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
wbm <= wbm_adr0;
else
if ((wbm==wbm_adr0 & !b_fifo_empty) |
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
(wbm==wbm_adr1 & !wbm_we_o) |
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
assign b_d = {wbm_dat_i,4'b1111};
assign b_wr = !wbm_we_o & wbm_ack_i;
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1'b0;
assign b_rd = b_rd_adr | b_rd_data;
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
cnt_shreg_ce_clear # ( .length(16))
cnt1 (
.cke(wbm_ack_i),
.clear(wbm_eoc),
.q(wbm_count),
.rst(wbm_rst),
.clk(wbm_clk));
assign wbm_cyc_o = wbm==wbm_data;
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
(wbm==wbm_data) ? 1'b1 :
1'b0;
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
else begin
if (wbm==wbm_adr0 & !b_fifo_empty)
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
else if (wbm_eoc_alert & wbm_ack_i)
wbm_cti_o <= endofburst;
end
//async_fifo_dw_simplex_top
vl_fifo_2r2w_async_simplex
# ( .data_width(36), .addr_width(addr_width))
fifo (
// a side
.a_d(a_d),
.a_wr(a_wr),
.a_fifo_full(a_fifo_full),
.a_q(a_q),
.a_rd(a_rd),
.a_fifo_empty(a_fifo_empty),
.a_clk(wbs_clk),
.a_rst(wbs_rst),
// b side
.b_d(b_d),
.b_wr(b_wr),
.b_fifo_full(b_fifo_full),
.b_q(b_q),
.b_rd(b_rd),
.b_fifo_empty(b_fifo_empty),
.b_clk(wbm_clk),
.b_rst(wbm_rst)
);
endmodule

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