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    /versatile_library/trunk
    from Rev 125 to Rev 126
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Rev 125 → Rev 126

/rtl/verilog/versatile_library.v
6155,17 → 6155,17
parameter dw_m = dw_s;
//localparam aw_m = dw_s * aw_s / dw_m;
localparam aw_m =
(dw_s==dw_m) ? aw_m :
(dw_s==dw_m*2) ? aw_m+1 :
(dw_s==dw_m*4) ? aw_m+2 :
(dw_s==dw_m*8) ? aw_m+3 :
(dw_s==dw_m*16) ? aw_m+4 :
(dw_s==dw_m*32) ? aw_m+5 :
(dw_s==dw_m/2) ? aw_m-1 :
(dw_s==adw_m/4) ? aw_m-2 :
(dw_s==dw_m/8) ? aw_m-3 :
(dw_s==dw_m/16) ? aw_m-4 :
(dw_s==dw_m/32) ? aw_m-5 : 0;
(dw_s==dw_m) ? aw_s :
(dw_s==dw_m*2) ? aw_s+1 :
(dw_s==dw_m*4) ? aw_s+2 :
(dw_s==dw_m*8) ? aw_s+3 :
(dw_s==dw_m*16) ? aw_s+4 :
(dw_s==dw_m*32) ? aw_s+5 :
(dw_s==dw_m/2) ? aw_s-1 :
(dw_s==adw_m/4) ? aw_s-2 :
(dw_s==dw_m/8) ? aw_s-3 :
(dw_s==dw_m/16) ? aw_s-4 :
(dw_s==dw_m/32) ? aw_s-5 : 0;
 
parameter wbs_max_burst_width = 4;
parameter wbs_mode = "B3";
/rtl/verilog/versatile_library_actel.v
2856,17 → 2856,17
parameter dw_m = dw_s;
//localparam aw_m = dw_s * aw_s / dw_m;
localparam aw_m =
(dw_s==dw_m) ? aw_m :
(dw_s==dw_m*2) ? aw_m+1 :
(dw_s==dw_m*4) ? aw_m+2 :
(dw_s==dw_m*8) ? aw_m+3 :
(dw_s==dw_m*16) ? aw_m+4 :
(dw_s==dw_m*32) ? aw_m+5 :
(dw_s==dw_m/2) ? aw_m-1 :
(dw_s==adw_m/4) ? aw_m-2 :
(dw_s==dw_m/8) ? aw_m-3 :
(dw_s==dw_m/16) ? aw_m-4 :
(dw_s==dw_m/32) ? aw_m-5 : 0;
(dw_s==dw_m) ? aw_s :
(dw_s==dw_m*2) ? aw_s+1 :
(dw_s==dw_m*4) ? aw_s+2 :
(dw_s==dw_m*8) ? aw_s+3 :
(dw_s==dw_m*16) ? aw_s+4 :
(dw_s==dw_m*32) ? aw_s+5 :
(dw_s==dw_m/2) ? aw_s-1 :
(dw_s==adw_m/4) ? aw_s-2 :
(dw_s==dw_m/8) ? aw_s-3 :
(dw_s==dw_m/16) ? aw_s-4 :
(dw_s==dw_m/32) ? aw_s-5 : 0;
parameter wbs_max_burst_width = 4;
parameter wbs_mode = "B3";
parameter async = 1; // wbs_clk != wbm_clk
/rtl/verilog/wb.v
1237,17 → 1237,17
parameter dw_m = dw_s;
//localparam aw_m = dw_s * aw_s / dw_m;
localparam aw_m =
(dw_s==dw_m) ? aw_m :
(dw_s==dw_m*2) ? aw_m+1 :
(dw_s==dw_m*4) ? aw_m+2 :
(dw_s==dw_m*8) ? aw_m+3 :
(dw_s==dw_m*16) ? aw_m+4 :
(dw_s==dw_m*32) ? aw_m+5 :
(dw_s==dw_m/2) ? aw_m-1 :
(dw_s==adw_m/4) ? aw_m-2 :
(dw_s==dw_m/8) ? aw_m-3 :
(dw_s==dw_m/16) ? aw_m-4 :
(dw_s==dw_m/32) ? aw_m-5 : 0;
(dw_s==dw_m) ? aw_s :
(dw_s==dw_m*2) ? aw_s+1 :
(dw_s==dw_m*4) ? aw_s+2 :
(dw_s==dw_m*8) ? aw_s+3 :
(dw_s==dw_m*16) ? aw_s+4 :
(dw_s==dw_m*32) ? aw_s+5 :
(dw_s==dw_m/2) ? aw_s-1 :
(dw_s==adw_m/4) ? aw_s-2 :
(dw_s==dw_m/8) ? aw_s-3 :
(dw_s==dw_m/16) ? aw_s-4 :
(dw_s==dw_m/32) ? aw_s-5 : 0;
 
parameter wbs_max_burst_width = 4;
parameter wbs_mode = "B3";
/rtl/verilog/versatile_library_altera.v
2961,17 → 2961,17
parameter dw_m = dw_s;
//localparam aw_m = dw_s * aw_s / dw_m;
localparam aw_m =
(dw_s==dw_m) ? aw_m :
(dw_s==dw_m*2) ? aw_m+1 :
(dw_s==dw_m*4) ? aw_m+2 :
(dw_s==dw_m*8) ? aw_m+3 :
(dw_s==dw_m*16) ? aw_m+4 :
(dw_s==dw_m*32) ? aw_m+5 :
(dw_s==dw_m/2) ? aw_m-1 :
(dw_s==adw_m/4) ? aw_m-2 :
(dw_s==dw_m/8) ? aw_m-3 :
(dw_s==dw_m/16) ? aw_m-4 :
(dw_s==dw_m/32) ? aw_m-5 : 0;
(dw_s==dw_m) ? aw_s :
(dw_s==dw_m*2) ? aw_s+1 :
(dw_s==dw_m*4) ? aw_s+2 :
(dw_s==dw_m*8) ? aw_s+3 :
(dw_s==dw_m*16) ? aw_s+4 :
(dw_s==dw_m*32) ? aw_s+5 :
(dw_s==dw_m/2) ? aw_s-1 :
(dw_s==adw_m/4) ? aw_s-2 :
(dw_s==dw_m/8) ? aw_s-3 :
(dw_s==dw_m/16) ? aw_s-4 :
(dw_s==dw_m/32) ? aw_s-5 : 0;
parameter wbs_max_burst_width = 4;
parameter wbs_mode = "B3";
parameter async = 1; // wbs_clk != wbm_clk

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