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    /versatile_library/trunk
    from Rev 3 to Rev 4
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Rev 3 → Rev 4

/rtl/verilog/cnt_gray_bin_ce.csv File deleted
/rtl/verilog/cnt_gray.csv File deleted
/rtl/verilog/cnt_bin_ce_clear.csv
0,0 → 1,14
Name,type,,,,
cnt_bin_ce_clear,binary,,,,
,,,,,
clear,set,cke,rew,,
1,0,1,0,,
,,,,,
q,q_bin,z,zq,level1,level2
1,1,0,0,0,0
,,,,,
wrap,wrap_around,,,,
0,1,,,,
,,,,,
length,clear_value,set_value,wrap_value,level1,level2
4,0,1,0,15,
/rtl/verilog/cnt_lfsr_ce_rew_l1.csv
0,0 → 1,14
Name,type,,,,
cnt_lfsr_ce_rew_l1,LFSR,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,1,,
,,,,,
q,q_bin,z,zq,level1,level2
0,1,0,0,1,0
,,,,,
wrap,wrap_around,,,,
1,1,,,,
,,,,,
length,clear_value,set_value,wrap_value,level1,level2
4,0,1,8,15,
/rtl/verilog/cnt_lfsr_ce_zq.csv
0,0 → 1,14
Name,type,,,,
cnt_lfsr_ce_zq,LFSR,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,0,,
,,,,,
q,q_bin,z,zq,level1,level2
0,1,0,1,0,0
,,,,,
wrap,wrap_around,,,,
1,1,,,,
,,,,,
length,clear_value,set_value,wrap_value,level1,level2
4,0,1,8,15,
/rtl/verilog/cnt_bin_ce_rew_l1.csv
0,0 → 1,14
Name,type,,,,
cnt_bin_ce_rew_l1,binary,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,1,,
,,,,,
q,q_bin,z,zq,level1,level2
0,1,0,0,1,0
,,,,,
wrap,wrap_around,,,,
0,1,,,,
,,,,,
length,clear_value,set_value,wrap_value,level1,level2
4,0,1,1,15,
/rtl/verilog/cnt_gray_ce_bin.csv
0,0 → 1,14
Name,type,,,,
cnt_gray_ce_bin,GRAY,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,0,,
,,,,,
q,q_bin,z,zq,level1,level2
1,1,0,0,0,0
,,,,,
wrap,wrap_around,,,,
0,1,,,,
,,,,,
length,clear_value,set_value,wrap_value,level1,level2
4,0,1,8,15,
/rtl/verilog/clk_and_reset.v
40,12 → 40,9
//// ////
//////////////////////////////////////////////////////////////////////
 
`define EXPAND_TO_IFDEF `ifdef
`define EXPAND_TO_ELSE `else
`define EXPAND_TO_ENDIF `endif
// Global buffer
// usage:
// use to enable global buffers for high fan out signal such as clock and reset
// use to enable global buffers for high fan out signals such as clock and reset
 
`ifdef ACTEL
 
66,7 → 63,11
module vl_gbuf ( i, o);
input i;
output o;
//E2_ifdef SIM_GBUF
assign o=i;
//E2_else
gbuf gbuf_i0 ( .CLK(i), .GL(o));
//E2_endif
endmodule
`else
`ifdef ALTERA
73,7 → 74,7
altera
`else
 
`timescale 1 ns/1 ns
`timescale 1 ns/100 ps
module vl_gbuf ( i, o);
input i;
output o;
85,7 → 86,7
// sync reset
// input active lo async reset, normally from external reset generetaor and/or switch
// output active high global reset sync with two DFFs
`timescale 1 ns/1 ns
`timescale 1 ns/100 ps
module vl_sync_rst ( rst_n_i, rst_o, clk);
input rst_n_i, clk;
output rst_o;
100,13 → 101,14
 
// vl_pll
`ifdef ACTEL
`timescale 1 ns/100 ps
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
parameter index = 0;
parameter number_of_clk = 3;
parameter clk_i_period_time = 20;
parameter [0:number_of_clk-1] mult = {32'd1,32'd2,32'd2};
parameter [0:number_of_clk-1] div = {32'd1,32'd3,32'd3};
parameter lock_delay = 200;
parameter number_of_clk = 1;
parameter period_time_0 = 20;
parameter period_time_1 = 20;
parameter period_time_2 = 20;
parameter lock_delay = 2000;
input clk_i, rst_n_i;
output lock;
output reg [0:number_of_clk-1] clk_o;
114,16 → 116,27
 
//E2_ifdef SIM_PLL
 
always
#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
 
generate if (number_of_clk > 1)
always
#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
endgenerate
 
generate if (number_of_clk > 2)
always
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
endgenerate
 
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
always
#((clk_i_period_time*div[i]/mult[i])/2) clk_o[i] <= (!rst_n_i) ? 0 : ~clk_o[i];
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
end
endgenerate
 
assign #lock_delay lock = rst_n_i;
 
endmodule
//E2_else
generate if (number_of_clk==1 & index==0) begin
192,14 → 205,13
`else
 
// generic PLL
`timescale 1 ns/100 ps
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
parameter index = 0;
parameter number_of_clk = 3;
parameter clk_i_period_time = 20;
parameter clk0_feedthrough = 0;
parameter mult = 1;
parameter div = 1;
parameter [0:number_of_clk-1] post_div = {32'd1,32'd3,32'd3};
parameter number_of_clk = 1;
parameter period_time_0 = 20;
parameter period_time_1 = 20;
parameter period_time_2 = 20;
parameter lock_delay = 2000;
input clk_i, rst_n_i;
output lock;
206,12 → 218,21
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
 
always
#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
 
generate if (number_of_clk > 1)
always
#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
endgenerate
 
generate if (number_of_clk > 2)
always
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
endgenerate
 
genvar i;
generate if (clk0_feedthrough==1) begin: clk0_feedthrough
always #(clk_i_period_time/2+0.200) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
generate for (i=clk0_feedthrough;i<number_of_clk;i=i+1) begin: clock
always
#((clk_i_period_time*div/mult*post_div[i])/2) clk_o[i] <= (!rst_n_i) ? 0 : ~clk_o[i];
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
end
endgenerate
/rtl/verilog/counters.v
40,3 → 40,42
//// ////
//////////////////////////////////////////////////////////////////////
 
module cnt_shreg_ce ( cke, q, rst, clk);
 
parameter length = 4;
input cke;
output reg [0:length-1] q;
input rst;
input clk;
 
always @ (posedge clk or posedge rst)
if (rst)
q <= {1'b1,{length-1{1'b0}}};
else
if (cke)
q <= q >> 1;
endmodule
 
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
 
parameter length = 4;
input cke;
input clear;
output reg [0:length-1] q;
input rst;
input clk;
 
always @ (posedge clk or posedge rst)
if (rst)
q <= {1'b1,{length-1{1'b0}}};
else
if (cke)
if (clear)
q <= {1'b1,{length-1{1'b0}}};
else
q <= q >> 1;
endmodule
 
 
/rtl/verilog/cnt_bin_ce_clear_set_rew.csv
0,0 → 1,14
Name,type,,,,
cnt_bin_ce_clear_set_rew,binary,,,,
,,,,,
clear,set,cke,rew,,
1,1,1,1,,
,,,,,
q,q_bin,z,zq,level1,level2
1,1,0,0,0,0
,,,,,
wrap,wrap_around,,,,
0,1,,,,
,,,,,
length,clear_value,set_value,wrap_value,level1,level2
4,0,1,0,15,
/rtl/verilog/Makefile
1,11 → 1,16
VERILOG_FILES = clk_and_reset.v
VERILOG_FILES += registers.v
 
VERILOG_FILES_CNT = cnt_lfsr.v
VERILOG_FILES_CNT += cnt_lfsr_ce.v
VERILOG_FILES_CNT = cnt_bin_ce.v
VERILOG_FILES_CNT += cnt_bin_ce_clear.v
VERILOG_FILES_CNT += cnt_bin_ce_clear_set_rew.v
VERILOG_FILES_CNT += cnt_bin_ce_rew_l1.v
VERILOG_FILES_CNT += cnt_lfsr_zq.v
VERILOG_FILES_CNT += cnt_lfsr_ce_zq.v
VERILOG_FILES_CNT += cnt_lfsr_ce_rew_l1.v
VERILOG_FILES_CNT += cnt_gray.v
VERILOG_FILES_CNT += cnt_gray_ce.v
VERILOG_FILES_CNT += cnt_gray_bin_ce.v
VERILOG_FILES_CNT += cnt_gray_ce_bin.v
 
VERILOG_FILES += $(VERILOG_FILES_CNT)
VERILOG_FILES += counters.v
20,11 → 25,15
 
#.PHONY: $(VERILOG_FILES_CNT)
$(VERILOG_FILES_CNT):
./versatile_counter_generator.php cnt_lfsr.csv > cnt_lfsr.v
./versatile_counter_generator.php cnt_lfsr_ce.csv > cnt_lfsr_ce.v
./versatile_counter_generator.php cnt_gray.csv > cnt_gray.v
./versatile_counter_generator.php cnt_bin_ce.csv > cnt_bin_ce.v
./versatile_counter_generator.php cnt_bin_ce_clear.csv > cnt_bin_ce_clear.v
./versatile_counter_generator.php cnt_bin_ce_clear_set_rew.csv > cnt_bin_ce_clear_set_rew.v
./versatile_counter_generator.php cnt_bin_ce_rew_l1.csv > cnt_bin_ce_rew_l1.v
./versatile_counter_generator.php cnt_lfsr_zq.csv > cnt_lfsr_zq.v
./versatile_counter_generator.php cnt_lfsr_ce_zq.csv > cnt_lfsr_ce_zq.v
./versatile_counter_generator.php cnt_lfsr_ce_rew_l1.csv > cnt_lfsr_ce_rew_l1.v
./versatile_counter_generator.php cnt_gray_ce.csv > cnt_gray_ce.v
./versatile_counter_generator.php cnt_gray_bin_ce.csv > cnt_gray_bin_ce.v
./versatile_counter_generator.php cnt_gray_ce_bin.csv > cnt_gray_ce_bin.v
 
versatile_library.v: $(VERILOG_FILES)
cat $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > versatile_library.v
/rtl/verilog/cnt_bin_ce.csv
0,0 → 1,14
Name,type,,,,
cnt_bin_ce,binary,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,0,,
,,,,,
q,q_bin,z,zq,level1,level2
1,1,0,0,0,0
,,,,,
wrap,wrap_around,,,,
0,1,,,,
,,,,,
length,clear_value,set_value,wrap_value,level1,level2
4,0,1,0,15,
/rtl/verilog/cnt_lfsr_zq.csv
0,0 → 1,14
Name,type,,,,
cnt_lfsr_zq,LFSR,,,,
,,,,,
clear,set,cke,rew,,
0,0,0,0,,
,,,,,
q,q_bin,z,zq,level1,level2
0,1,0,1,0,0
,,,,,
wrap,wrap_around,,,,
1,1,,,,
,,,,,
length,clear_value,set_value,wrap_value,level1,level2
4,0,1,8,15,
/doc/src/Versatile_library.odt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/Versatile_library.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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