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Rev 33 → Rev 34

/rtl/verilog/versatile_library.v
844,7 → 844,47
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_mux2_andor ( a1, a0, sel, dout);
 
parameter width = 32;
parameter nr_of_ports = 2;
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
 
// or
assign dout = tmp[1] | tmp[0];
 
endmodule
 
module vl_mux3_andor ( a2, a1, a0, sel, dout);
 
parameter width = 32;
parameter nr_of_ports = 3;
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
 
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
 
endmodule
 
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
 
parameter width = 32;
/rtl/verilog/versatile_library_actel.v
437,6 → 437,35
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_mux2_andor ( a1, a0, sel, dout);
parameter width = 32;
parameter nr_of_ports = 2;
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
// or
assign dout = tmp[1] | tmp[0];
endmodule
module vl_mux3_andor ( a2, a1, a0, sel, dout);
parameter width = 32;
parameter nr_of_ports = 3;
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
endmodule
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter nr_of_ports = 4;
/rtl/verilog/versatile_library_altera.v
545,6 → 545,35
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_mux2_andor ( a1, a0, sel, dout);
parameter width = 32;
parameter nr_of_ports = 2;
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
// or
assign dout = tmp[1] | tmp[0];
endmodule
module vl_mux3_andor ( a2, a1, a0, sel, dout);
parameter width = 32;
parameter nr_of_ports = 3;
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
endmodule
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter nr_of_ports = 4;
/rtl/verilog/logic.v
39,7 → 39,47
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_mux2_andor ( a1, a0, sel, dout);
 
parameter width = 32;
parameter nr_of_ports = 2;
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
 
// or
assign dout = tmp[1] | tmp[0];
 
endmodule
 
module vl_mux3_andor ( a2, a1, a0, sel, dout);
 
parameter width = 32;
parameter nr_of_ports = 3;
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
 
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
 
endmodule
 
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
 
parameter width = 32;

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