URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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- This comparison shows the changes necessary to convert path
/versatile_library/trunk
- from Rev 51 to Rev 52
- ↔ Reverse comparison
Rev 51 → Rev 52
/rtl/verilog/versatile_library.v
4643,7 → 4643,7
module `BASE`MODULE ( |
`undef MODULE |
wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst); |
wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst); |
|
parameter dat_width = 32; |
parameter adr_width = 8; |
4654,9 → 4654,10
input wb_we_i, wb_stb_i, wb_cyc_i; |
output [dat_width-1:0] wb_dat_o; |
reg [dat_width-1:0] wb_dat_o; |
output stall_o; |
output wb_stall_o; |
output wb_ack_o; |
reg wb_ack_o; |
reg wb_ack_o; |
input wb_clk, wb_rst; |
|
generate |
4676,6 → 4677,14
end |
endgenerate |
|
always @ (posedge wb_clk or posedge wb_rst) |
if (rst) |
wb_ack_o <= 1'b0; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i |
|
assign wb_stall_o = 1'b0; |
|
endmodule |
`endif |
|
/rtl/verilog/versatile_library_actel.v
1946,7 → 1946,7
// WB RAM with byte enable |
module vl_wb_b4_ram_be ( |
wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst); |
wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst); |
parameter dat_width = 32; |
parameter adr_width = 8; |
input [dat_width-1:0] wb_dat_i; |
1955,9 → 1955,10
input wb_we_i, wb_stb_i, wb_cyc_i; |
output [dat_width-1:0] wb_dat_o; |
reg [dat_width-1:0] wb_dat_o; |
output stall_o; |
output wb_stall_o; |
output wb_ack_o; |
reg wb_ack_o; |
reg wb_ack_o; |
input wb_clk, wb_rst; |
generate |
if (dat_width==32) begin |
1975,6 → 1976,12
end |
end |
endgenerate |
always @ (posedge wb_clk or posedge wb_rst) |
if (rst) |
wb_ack_o <= 1'b0; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i |
assign wb_stall_o = 1'b0; |
endmodule |
// WB ROM |
module vl_wb_b4_rom ( |
/rtl/verilog/wb.v
473,7 → 473,7
module `BASE`MODULE ( |
`undef MODULE |
wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst); |
wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst); |
|
parameter dat_width = 32; |
parameter adr_width = 8; |
484,9 → 484,10
input wb_we_i, wb_stb_i, wb_cyc_i; |
output [dat_width-1:0] wb_dat_o; |
reg [dat_width-1:0] wb_dat_o; |
output stall_o; |
output wb_stall_o; |
output wb_ack_o; |
reg wb_ack_o; |
reg wb_ack_o; |
input wb_clk, wb_rst; |
|
generate |
506,6 → 507,14
end |
endgenerate |
|
always @ (posedge wb_clk or posedge wb_rst) |
if (rst) |
wb_ack_o <= 1'b0; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i |
|
assign wb_stall_o = 1'b0; |
|
endmodule |
`endif |
|
/rtl/verilog/versatile_library_altera.v
2051,7 → 2051,7
// WB RAM with byte enable |
module vl_wb_b4_ram_be ( |
wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst); |
wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst); |
parameter dat_width = 32; |
parameter adr_width = 8; |
input [dat_width-1:0] wb_dat_i; |
2060,9 → 2060,10
input wb_we_i, wb_stb_i, wb_cyc_i; |
output [dat_width-1:0] wb_dat_o; |
reg [dat_width-1:0] wb_dat_o; |
output stall_o; |
output wb_stall_o; |
output wb_ack_o; |
reg wb_ack_o; |
reg wb_ack_o; |
input wb_clk, wb_rst; |
generate |
if (dat_width==32) begin |
2080,6 → 2081,12
end |
end |
endgenerate |
always @ (posedge wb_clk or posedge wb_rst) |
if (rst) |
wb_ack_o <= 1'b0; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i |
assign wb_stall_o = 1'b0; |
endmodule |
// WB ROM |
module vl_wb_b4_rom ( |