URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library/trunk
- from Rev 79 to Rev 80
- ↔ Reverse comparison
Rev 79 → Rev 80
/rtl/verilog/versatile_library.v
4923,7 → 4923,7
output [31:2] address; |
output [3:0] be; |
output write; |
output read; |
output reg read; |
output beginbursttransfer; |
output [3:0] burstcount; |
input readdatavalid; |
4947,7 → 4947,7
if (rst) |
read <= 1'b0; |
else |
if (!last_cyc & wbm_cyc_o) |
if (!last_cyc & wbm_cyc_o & !wbm_we_o) |
read <= 1'b1; |
else if (!waitrequest) |
read <= 1'b0; |
4962,18 → 4962,17
always @ (posedge clk or posedge rst) |
if (rst) begin |
counter <= 4'd0; |
write <= 1'b0; |
end else |
if (!waitrequest & last_cyc & wbm_cyc_o) begin |
write <= 1'b1; |
counter <= burstcount -1; |
end else if (waitrequest & last_cyc & wbm_cyc_o) begin |
write <= 1'b1; |
counter <= burstcount; |
end else if (!waitrequst) begin |
counter <= counter - 4'd1; |
write <= (counter!=4'd0 & wbm_stb_o) |
if (wbm_we_o) begin |
if (!waitrequest & !last_cyc & wbm_cyc_o) begin |
counter <= burstcount -1; |
end else if (waitrequest & !last_cyc & wbm_cyc_o) begin |
counter <= burstcount; |
end else if (!waitrequest & wbm_stb_o) begin |
counter <= counter - 4'd1; |
end |
end |
assign write = wbm_cyc & wbm_stb_o & wbm_we_o & counter!=4'd0; |
|
`define MODULE wb3wb3_bridge |
`BASE`MODULE wbwb3inst ( |
/rtl/verilog/versatile_library_actel.v
2136,7 → 2136,7
output [31:2] address; |
output [3:0] be; |
output write; |
output read; |
output reg read; |
output beginbursttransfer; |
output [3:0] burstcount; |
input readdatavalid; |
2157,7 → 2157,7
if (rst) |
read <= 1'b0; |
else |
if (!last_cyc & wbm_cyc_o) |
if (!last_cyc & wbm_cyc_o & !wbm_we_o) |
read <= 1'b1; |
else if (!waitrequest) |
read <= 1'b0; |
2170,18 → 2170,17
always @ (posedge clk or posedge rst) |
if (rst) begin |
counter <= 4'd0; |
write <= 1'b0; |
end else |
if (!waitrequest & last_cyc & wbm_cyc_o) begin |
write <= 1'b1; |
counter <= burstcount -1; |
end else if (waitrequest & last_cyc & wbm_cyc_o) begin |
write <= 1'b1; |
counter <= burstcount; |
end else if (!waitrequst) begin |
counter <= counter - 4'd1; |
write <= (counter!=4'd0 & wbm_stb_o) |
if (wbm_we_o) begin |
if (!waitrequest & !last_cyc & wbm_cyc_o) begin |
counter <= burstcount -1; |
end else if (waitrequest & !last_cyc & wbm_cyc_o) begin |
counter <= burstcount; |
end else if (!waitrequest & wbm_stb_o) begin |
counter <= counter - 4'd1; |
end |
end |
assign write = wbm_cyc & wbm_stb_o & wbm_we_o & counter!=4'd0; |
vl_wb3wb3_bridge wbwb3inst ( |
// wishbone slave side |
.wbs_dat_i(wbs_dat_i), |
/rtl/verilog/wb.v
328,7 → 328,7
output [31:2] address; |
output [3:0] be; |
output write; |
output read; |
output reg read; |
output beginbursttransfer; |
output [3:0] burstcount; |
input readdatavalid; |
352,7 → 352,7
if (rst) |
read <= 1'b0; |
else |
if (!last_cyc & wbm_cyc_o) |
if (!last_cyc & wbm_cyc_o & !wbm_we_o) |
read <= 1'b1; |
else if (!waitrequest) |
read <= 1'b0; |
367,18 → 367,17
always @ (posedge clk or posedge rst) |
if (rst) begin |
counter <= 4'd0; |
write <= 1'b0; |
end else |
if (!waitrequest & last_cyc & wbm_cyc_o) begin |
write <= 1'b1; |
counter <= burstcount -1; |
end else if (waitrequest & last_cyc & wbm_cyc_o) begin |
write <= 1'b1; |
counter <= burstcount; |
end else if (!waitrequst) begin |
counter <= counter - 4'd1; |
write <= (counter!=4'd0 & wbm_stb_o) |
if (wbm_we_o) begin |
if (!waitrequest & !last_cyc & wbm_cyc_o) begin |
counter <= burstcount -1; |
end else if (waitrequest & !last_cyc & wbm_cyc_o) begin |
counter <= burstcount; |
end else if (!waitrequest & wbm_stb_o) begin |
counter <= counter - 4'd1; |
end |
end |
assign write = wbm_cyc & wbm_stb_o & wbm_we_o & counter!=4'd0; |
|
`define MODULE wb3wb3_bridge |
`BASE`MODULE wbwb3inst ( |
/rtl/verilog/versatile_library_altera.v
2241,7 → 2241,7
output [31:2] address; |
output [3:0] be; |
output write; |
output read; |
output reg read; |
output beginbursttransfer; |
output [3:0] burstcount; |
input readdatavalid; |
2262,7 → 2262,7
if (rst) |
read <= 1'b0; |
else |
if (!last_cyc & wbm_cyc_o) |
if (!last_cyc & wbm_cyc_o & !wbm_we_o) |
read <= 1'b1; |
else if (!waitrequest) |
read <= 1'b0; |
2275,18 → 2275,17
always @ (posedge clk or posedge rst) |
if (rst) begin |
counter <= 4'd0; |
write <= 1'b0; |
end else |
if (!waitrequest & last_cyc & wbm_cyc_o) begin |
write <= 1'b1; |
counter <= burstcount -1; |
end else if (waitrequest & last_cyc & wbm_cyc_o) begin |
write <= 1'b1; |
counter <= burstcount; |
end else if (!waitrequst) begin |
counter <= counter - 4'd1; |
write <= (counter!=4'd0 & wbm_stb_o) |
if (wbm_we_o) begin |
if (!waitrequest & !last_cyc & wbm_cyc_o) begin |
counter <= burstcount -1; |
end else if (waitrequest & !last_cyc & wbm_cyc_o) begin |
counter <= burstcount; |
end else if (!waitrequest & wbm_stb_o) begin |
counter <= counter - 4'd1; |
end |
end |
assign write = wbm_cyc & wbm_stb_o & wbm_we_o & counter!=4'd0; |
vl_wb3wb3_bridge wbwb3inst ( |
// wishbone slave side |
.wbs_dat_i(wbs_dat_i), |