URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library/trunk
- from Rev 8 to Rev 7
- ↔ Reverse comparison
Rev 8 → Rev 7
/rtl/verilog/versatile_library.v
344,27 → 344,6
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endmodule |
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module dff_ce_clear ( d, ce, clear, q, clk, rst); |
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parameter width = 1; |
parameter reset_value = 0; |
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input [width-1:0] d; |
input ce, clk, rst; |
output reg [width-1:0] q; |
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always @ (posedge clk or posedge rst) |
if (rst) |
q <= reset_value; |
else |
if (ce) |
if (clear) |
q <= {width{1'b0}}; |
else |
q <= d; |
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endmodule |
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`ifdef ALTERA |
// megafunction wizard: %LPM_FF% |
// GENERATION: STANDARD |
1989,7 → 1968,7
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endmodule |
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module vl_fifo_2r2w_async ( |
module vl_fifo_2r2w ( |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
2037,7 → 2016,7
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endmodule |
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module vl_fifo_2r2w_async_simplex ( |
module vl_fifo_2r2w_simplex ( |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
/rtl/verilog/versatile_library_actel.v
252,22 → 252,6
if (ce) |
q <= d; |
endmodule |
module dff_ce_clear ( d, ce, clear, q, clk, rst); |
parameter width = 1; |
parameter reset_value = 0; |
input [width-1:0] d; |
input ce, clk, rst; |
output reg [width-1:0] q; |
always @ (posedge clk or posedge rst) |
if (rst) |
q <= reset_value; |
else |
if (ce) |
if (clear) |
q <= {width{1'b0}}; |
else |
q <= d; |
endmodule |
module dff_sr ( aclr, aset, clock, data, q); |
input aclr; |
input aset; |
1581,7 → 1565,7
# (.addr_width(addr_width)) |
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) ); |
endmodule |
module vl_fifo_2r2w_async ( |
module vl_fifo_2r2w ( |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
1622,7 → 1606,7
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst) |
); |
endmodule |
module vl_fifo_2r2w_async_simplex ( |
module vl_fifo_2r2w_simplex ( |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
/rtl/verilog/versatile_library_altera.v
149,22 → 149,6
if (ce) |
q <= d; |
endmodule |
module dff_ce_clear ( d, ce, clear, q, clk, rst); |
parameter width = 1; |
parameter reset_value = 0; |
input [width-1:0] d; |
input ce, clk, rst; |
output reg [width-1:0] q; |
always @ (posedge clk or posedge rst) |
if (rst) |
q <= reset_value; |
else |
if (ce) |
if (clear) |
q <= {width{1'b0}}; |
else |
q <= d; |
endmodule |
// megafunction wizard: %LPM_FF% |
// GENERATION: STANDARD |
// VERSION: WM1.0 |
1567,7 → 1551,7
# (.addr_width(addr_width)) |
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) ); |
endmodule |
module vl_fifo_2r2w_async ( |
module vl_fifo_2r2w ( |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
1608,7 → 1592,7
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst) |
); |
endmodule |
module vl_fifo_2r2w_async_simplex ( |
module vl_fifo_2r2w_simplex ( |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
/rtl/verilog/registers.v
100,27 → 100,6
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endmodule |
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module dff_ce_clear ( d, ce, clear, q, clk, rst); |
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parameter width = 1; |
parameter reset_value = 0; |
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input [width-1:0] d; |
input ce, clk, rst; |
output reg [width-1:0] q; |
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always @ (posedge clk or posedge rst) |
if (rst) |
q <= reset_value; |
else |
if (ce) |
if (clear) |
q <= {width{1'b0}}; |
else |
q <= d; |
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endmodule |
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`ifdef ALTERA |
// megafunction wizard: %LPM_FF% |
// GENERATION: STANDARD |