OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /versatile_library
    from Rev 113 to Rev 114
    Reverse comparison

Rev 113 → Rev 114

/trunk/rtl/verilog/versatile_library.v
116,15 → 116,6
`endif
`endif
 
`ifdef WB_RAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
171,12 → 162,6
`endif
`endif
 
`ifdef WB_SHADOW_RAM
`ifndef WB_RAM_BE
`define WB_RAM_BE
`endif
`endif
 
`ifdef WB_CACHE
`ifndef RAM
`define RAM
199,8 → 184,8
`endif
 
`ifdef WB_SHADOW_RAM
`ifndef WB_RAM
`define WB_RAM
`ifndef WB_RAM_BE
`define WB_RAM_BE
`endif
`endif
 
208,8 → 193,11
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS
/trunk/rtl/verilog/defines.v
116,15 → 116,6
`endif
`endif
 
`ifdef WB_RAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
171,12 → 162,6
`endif
`endif
 
`ifdef WB_SHADOW_RAM
`ifndef WB_RAM_BE
`define WB_RAM_BE
`endif
`endif
 
`ifdef WB_CACHE
`ifndef RAM
`define RAM
199,8 → 184,8
`endif
 
`ifdef WB_SHADOW_RAM
`ifndef WB_RAM
`define WB_RAM
`ifndef WB_RAM_BE
`define WB_RAM_BE
`endif
`endif
 
208,8 → 193,11
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.