URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library
- from Rev 114 to Rev 113
- ↔ Reverse comparison
Rev 114 → Rev 113
/trunk/rtl/verilog/versatile_library.v
116,6 → 116,15
`endif |
`endif |
|
`ifdef WB_RAM |
`ifndef WB_ADR_INC |
`define WB_ADR_INC |
`endif |
`ifndef RAM_BE |
`define RAM_BE |
`endif |
`endif |
|
`ifdef WB3_ARBITER_TYPE1 |
`ifndef SPR |
`define SPR |
162,6 → 171,12
`endif |
`endif |
|
`ifdef WB_SHADOW_RAM |
`ifndef WB_RAM_BE |
`define WB_RAM_BE |
`endif |
`endif |
|
`ifdef WB_CACHE |
`ifndef RAM |
`define RAM |
184,8 → 199,8
`endif |
|
`ifdef WB_SHADOW_RAM |
`ifndef WB_RAM_BE |
`define WB_RAM_BE |
`ifndef WB_RAM |
`define WB_RAM |
`endif |
`endif |
|
193,11 → 208,8
`ifndef WB_ADR_INC |
`define WB_ADR_INC |
`endif |
`ifndef RAM_BE |
`define RAM_BE |
`endif |
`endif |
|
|
`ifdef MULTS18X18 |
`ifndef MULTS |
`define MULTS |
/trunk/rtl/verilog/defines.v
116,6 → 116,15
`endif |
`endif |
|
`ifdef WB_RAM |
`ifndef WB_ADR_INC |
`define WB_ADR_INC |
`endif |
`ifndef RAM_BE |
`define RAM_BE |
`endif |
`endif |
|
`ifdef WB3_ARBITER_TYPE1 |
`ifndef SPR |
`define SPR |
162,6 → 171,12
`endif |
`endif |
|
`ifdef WB_SHADOW_RAM |
`ifndef WB_RAM_BE |
`define WB_RAM_BE |
`endif |
`endif |
|
`ifdef WB_CACHE |
`ifndef RAM |
`define RAM |
184,8 → 199,8
`endif |
|
`ifdef WB_SHADOW_RAM |
`ifndef WB_RAM_BE |
`define WB_RAM_BE |
`ifndef WB_RAM |
`define WB_RAM |
`endif |
`endif |
|
193,11 → 208,8
`ifndef WB_ADR_INC |
`define WB_ADR_INC |
`endif |
`ifndef RAM_BE |
`define RAM_BE |
`endif |
`endif |
|
|
`ifdef MULTS18X18 |
`ifndef MULTS |
`define MULTS |