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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library
    from Rev 140 to Rev 141
    Reverse comparison

Rev 140 → Rev 141

/trunk/rtl/verilog/versatile_library.v
174,6 → 174,9
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
4382,10 → 4385,10
if (debug==1) begin : debug_we
always @ (posedge clk_a)
if (we_a)
$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
$display ("Debug: Value %h written on port A at address %h : time %t", d_a, adr_a, $time);
always @ (posedge clk_b)
if (we_b)
$display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
$display ("Debug: Value %h written on port B at address %h : time %t", d_b, adr_b, $time);
end
endgenerate
 
/trunk/rtl/verilog/versatile_library_actel.v
2957,10 → 2957,10
if (debug==1) begin : debug_we
always @ (posedge clk_a)
if (we_a)
$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
$display ("Debug: Value %h written on port A at address %h : time %t", d_a, adr_a, $time);
always @ (posedge clk_b)
if (we_b)
$display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
$display ("Debug: Value %h written on port B at address %h : time %t", d_b, adr_b, $time);
end
endgenerate
`ifdef SYSTEMVERILOG
/trunk/rtl/verilog/versatile_library_altera.v
3052,10 → 3052,10
if (debug==1) begin : debug_we
always @ (posedge clk_a)
if (we_a)
$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
$display ("Debug: Value %h written on port A at address %h : time %t", d_a, adr_a, $time);
always @ (posedge clk_b)
if (we_b)
$display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
$display ("Debug: Value %h written on port B at address %h : time %t", d_b, adr_b, $time);
end
endgenerate
`ifdef SYSTEMVERILOG
/trunk/rtl/verilog/defines.v
174,6 → 174,9
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
/trunk/rtl/verilog/memories.v
475,10 → 475,10
if (debug==1) begin : debug_we
always @ (posedge clk_a)
if (we_a)
$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
$display ("Debug: Value %h written on port A at address %h : time %t", d_a, adr_a, $time);
always @ (posedge clk_b)
if (we_b)
$display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
$display ("Debug: Value %h written on port B at address %h : time %t", d_b, adr_b, $time);
end
endgenerate
 

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