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Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library
    from Rev 142 to Rev 143
    Reverse comparison

Rev 142 → Rev 143

/trunk/rtl/verilog/versatile_library.v
5001,6 → 5001,7
);
parameter data_width = 32;
parameter addr_width = 5;
parameter debug = 0;
input [addr_width-1:0] a1, a2, a3;
input [data_width-1:0] wd3;
input we3;
5007,6 → 5008,14
output [data_width-1:0] rd1, rd2;
input clk;
 
generate
if (debug==1) begin : debug_we
always @ (posedge clk)
if (we)
$display ("Value %h written at register %h : time %t", d, adr, $time);
end
endgenerate
 
`ifdef ACTEL
reg [data_width-1:0] wd3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
/trunk/rtl/verilog/versatile_library_actel.v
3400,11 → 3400,19
);
parameter data_width = 32;
parameter addr_width = 5;
parameter debug = 0;
input [addr_width-1:0] a1, a2, a3;
input [data_width-1:0] wd3;
input we3;
output [data_width-1:0] rd1, rd2;
input clk;
generate
if (debug==1) begin : debug_we
always @ (posedge clk)
if (we)
$display ("Value %h written at register %h : time %t", d, adr, $time);
end
endgenerate
reg [data_width-1:0] wd3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg we3_reg;
/trunk/rtl/verilog/versatile_library_altera.v
3495,11 → 3495,19
);
parameter data_width = 32;
parameter addr_width = 5;
parameter debug = 0;
input [addr_width-1:0] a1, a2, a3;
input [data_width-1:0] wd3;
input we3;
output [data_width-1:0] rd1, rd2;
input clk;
generate
if (debug==1) begin : debug_we
always @ (posedge clk)
if (we)
$display ("Value %h written at register %h : time %t", d, adr, $time);
end
endgenerate
vl_dpram_1r1w
# ( .data_width(data_width), .addr_width(addr_width))
ram1 (
/trunk/rtl/verilog/memories.v
1091,6 → 1091,7
);
parameter data_width = 32;
parameter addr_width = 5;
parameter debug = 0;
input [addr_width-1:0] a1, a2, a3;
input [data_width-1:0] wd3;
input we3;
1097,6 → 1098,14
output [data_width-1:0] rd1, rd2;
input clk;
 
generate
if (debug==1) begin : debug_we
always @ (posedge clk)
if (we)
$display ("Value %h written at register %h : time %t", d, adr, $time);
end
endgenerate
 
`ifdef ACTEL
reg [data_width-1:0] wd3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;

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