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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library
    from Rev 143 to Rev 144
    Reverse comparison

Rev 143 → Rev 144

/trunk/rtl/verilog/versatile_library.v
5011,7 → 5011,7
generate
if (debug==1) begin : debug_we
always @ (posedge clk)
if (we)
if (we3)
$display ("Value %h written at register %h : time %t", d, adr, $time);
end
endgenerate
/trunk/rtl/verilog/versatile_library_actel.v
3409,7 → 3409,7
generate
if (debug==1) begin : debug_we
always @ (posedge clk)
if (we)
if (we3)
$display ("Value %h written at register %h : time %t", d, adr, $time);
end
endgenerate
/trunk/rtl/verilog/versatile_library_altera.v
3504,7 → 3504,7
generate
if (debug==1) begin : debug_we
always @ (posedge clk)
if (we)
if (we3)
$display ("Value %h written at register %h : time %t", d, adr, $time);
end
endgenerate
/trunk/rtl/verilog/memories.v
1101,7 → 1101,7
generate
if (debug==1) begin : debug_we
always @ (posedge clk)
if (we)
if (we3)
$display ("Value %h written at register %h : time %t", d, adr, $time);
end
endgenerate

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