URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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- This comparison shows the changes necessary to convert path
/versatile_library
- from Rev 149 to Rev 148
- ↔ Reverse comparison
Rev 149 → Rev 148
/trunk/rtl/verilog/versatile_library.v
7371,14 → 7371,10
output [31:0] dout; |
|
parameter opcode_sll = 2'b00; |
parameter opcode_srl = 2'b01; |
//parameter opcode_srl = 2'b01; |
parameter opcode_sra = 2'b10; |
parameter opcode_ror = 2'b11; |
//parameter opcode_ror = 2'b11; |
|
parameter mult=0; // if set to 1 implemented based on multipliers which saves LUT |
|
generate |
if (mult==1) begin : impl_mult |
wire sll, sra; |
assign sll = opcode == opcode_sll; |
assign sra = opcode == opcode_sra; |
7448,23 → 7444,6
(s[4:3]==2'b01) ? tmp[1] : |
(s[4:3]==2'b10) ? tmp[2] : |
tmp[3]; |
end else begin : impl_classic |
reg [31:0] dout; |
`ifdef SYSTEMVERILOG |
always_comb |
`else |
always @ (din or s or opcode) |
`endif |
case (opcode) |
opcode_sll: dout = din << s; |
opcode_srl: dout = din >> s; |
opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}})); |
//opcode_ror: dout = not yet implemented |
default: dout = din << s; |
endcase |
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end |
engenerate |
|
endmodule |
`endif |
/trunk/rtl/verilog/versatile_library_actel.v
5105,12 → 5105,9
input [1:0] opcode; |
output [31:0] dout; |
parameter opcode_sll = 2'b00; |
parameter opcode_srl = 2'b01; |
//parameter opcode_srl = 2'b01; |
parameter opcode_sra = 2'b10; |
parameter opcode_ror = 2'b11; |
parameter mult=0; // if set to 1 implemented based on multipliers which saves LUT |
generate |
if (mult==1) begin : impl_mult |
//parameter opcode_ror = 2'b11; |
wire sll, sra; |
assign sll = opcode == opcode_sll; |
assign sra = opcode == opcode_sra; |
5171,22 → 5168,6
(s[4:3]==2'b01) ? tmp[1] : |
(s[4:3]==2'b10) ? tmp[2] : |
tmp[3]; |
end else begin : impl_classic |
reg [31:0] dout; |
`ifdef SYSTEMVERILOG |
always_comb |
`else |
always @ (din or s or opcode) |
`endif |
case (opcode) |
opcode_sll: dout = din << s; |
opcode_srl: dout = din >> s; |
opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}})); |
//opcode_ror: dout = not yet implemented |
default: dout = din << s; |
endcase |
end |
engenerate |
endmodule |
// logic unit |
// supporting the following logic functions |
/trunk/rtl/verilog/versatile_library_altera.v
5200,12 → 5200,9
input [1:0] opcode; |
output [31:0] dout; |
parameter opcode_sll = 2'b00; |
parameter opcode_srl = 2'b01; |
//parameter opcode_srl = 2'b01; |
parameter opcode_sra = 2'b10; |
parameter opcode_ror = 2'b11; |
parameter mult=0; // if set to 1 implemented based on multipliers which saves LUT |
generate |
if (mult==1) begin : impl_mult |
//parameter opcode_ror = 2'b11; |
wire sll, sra; |
assign sll = opcode == opcode_sll; |
assign sra = opcode == opcode_sra; |
5266,22 → 5263,6
(s[4:3]==2'b01) ? tmp[1] : |
(s[4:3]==2'b10) ? tmp[2] : |
tmp[3]; |
end else begin : impl_classic |
reg [31:0] dout; |
`ifdef SYSTEMVERILOG |
always_comb |
`else |
always @ (din or s or opcode) |
`endif |
case (opcode) |
opcode_sll: dout = din << s; |
opcode_srl: dout = din >> s; |
opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}})); |
//opcode_ror: dout = not yet implemented |
default: dout = din << s; |
endcase |
end |
engenerate |
endmodule |
// logic unit |
// supporting the following logic functions |
/trunk/rtl/verilog/arith.v
112,14 → 112,10
output [31:0] dout; |
|
parameter opcode_sll = 2'b00; |
parameter opcode_srl = 2'b01; |
//parameter opcode_srl = 2'b01; |
parameter opcode_sra = 2'b10; |
parameter opcode_ror = 2'b11; |
//parameter opcode_ror = 2'b11; |
|
parameter mult=0; // if set to 1 implemented based on multipliers which saves LUT |
|
generate |
if (mult==1) begin : impl_mult |
wire sll, sra; |
assign sll = opcode == opcode_sll; |
assign sra = opcode == opcode_sra; |
189,23 → 185,6
(s[4:3]==2'b01) ? tmp[1] : |
(s[4:3]==2'b10) ? tmp[2] : |
tmp[3]; |
end else begin : impl_classic |
reg [31:0] dout; |
//E2_ifdef SYSTEMVERILOG |
always_comb |
//E2_else |
always @ (din or s or opcode) |
//E2_endif |
case (opcode) |
opcode_sll: dout = din << s; |
opcode_srl: dout = din >> s; |
opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}})); |
//opcode_ror: dout = not yet implemented |
default: dout = din << s; |
endcase |
|
end |
engenerate |
|
endmodule |
`endif |