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/trunk/rtl/verilog/versatile_library.v
84,7 → 84,7
`endif //ACTEL |
|
// sync reset |
// input active lo async reset, normally from external reset generator and/or switch |
// input active lo async reset, normally from external reset generetaor and/or switch |
// output active high global reset sync with two DFFs |
`timescale 1 ns/100 ps |
module vl_sync_rst ( rst_n_i, rst_o, clk); |
93,22 → 93,22
reg [0:1] tmp; |
always @ (posedge clk or negedge rst_n_i) |
if (!rst_n_i) |
tmp <= 2'b11; |
tmp <= 2'b00; |
else |
tmp <= {1'b0,tmp[0]}; |
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o)); |
tmp <= {1'b1,tmp[0]}; |
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o)); |
endmodule |
|
// vl_pll |
`ifdef ACTEL |
`timescale 1 ps/1 ps |
`timescale 1 ns/100 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
parameter period_time_1 = 20000; |
parameter period_time_2 = 20000; |
parameter lock_delay = 2000000; |
parameter period_time_0 = 20; |
parameter period_time_1 = 20; |
parameter period_time_2 = 20; |
parameter lock_delay = 2000; |
input clk_i, rst_n_i; |
output lock; |
output reg [0:number_of_clk-1] clk_o; |
205,13 → 205,13
`else |
|
// generic PLL |
`timescale 1 ps/1 ps |
`timescale 1 ns/100 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
parameter period_time_1 = 20000; |
parameter period_time_2 = 20000; |
parameter period_time_0 = 20; |
parameter period_time_1 = 20; |
parameter period_time_2 = 20; |
parameter lock_delay = 2000; |
input clk_i, rst_n_i; |
output lock; |
242,8 → 242,7
endmodule |
|
`endif //altera |
`endif //actel |
////////////////////////////////////////////////////////////////////// |
`endif //actel////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile library, registers //// |
//// //// |
532,39 → 531,6
endmodule |
`endif |
|
module shreg ( d, q, clk, rst); |
parameter depth = 10; |
input d; |
output q; |
input clk, rst; |
|
reg [1:depth] dffs; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
|
module shreg_ce ( d, ce, q, clk, rst); |
parameter depth = 10; |
input d, ce; |
output q; |
input clk, rst; |
|
reg [1:depth] dffs; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
if (ce) |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
|
module delay ( d, q, clk, rst); |
parameter depth = 10; |
input d; |
579,25 → 545,7
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
|
module delay_emptyflag ( d, q, emptyflag, clk, rst); |
parameter depth = 10; |
input d; |
output q, emptyflag; |
input clk, rst; |
|
reg [1:depth] dffs; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
assign emptyflag = !(|dffs); |
endmodule |
////////////////////////////////////////////////////////////////////// |
endmodule////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
2422,49 → 2370,3
); |
|
endmodule |
|
// WB ROM |
module wb_boot_rom ( |
wb_adr_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_ack_o, wb_clk, wb_rst); |
|
`ifndef BOOT_ROM |
`define BOOT_ROM "boot_rom.v" |
`endif |
parameter addr_width = 5; |
|
input [(addr_width+2)-1:2] wb_adr_i; |
input wb_stb_i; |
input wb_cyc_i; |
output reg [31:0] wb_dat_o; |
output reg wb_ack_o; |
input wb_clk; |
input wb_rst; |
|
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_dat_o <= 32'h15000000; |
else |
case (wb_adr_i) |
`include `BOOT_ROM |
/* |
// Zero r0 and jump to 0x00000100 |
0 : wb_dat_o <= 32'h18000000; |
1 : wb_dat_o <= 32'hA8200000; |
2 : wb_dat_o <= 32'hA8C00100; |
3 : wb_dat_o <= 32'h44003000; |
4 : wb_dat_o <= 32'h15000000; |
*/ |
default: |
wb_dat_o <= 32'h00000000; |
|
endcase // case (wb_adr_i) |
|
|
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_ack_o <= 1'b0; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; |
|
endmodule |
/trunk/rtl/verilog/versatile_library_actel.v
64,7 → 64,7
endmodule |
//ACTEL |
// sync reset |
// input active lo async reset, normally from external reset generator and/or switch |
// input active lo async reset, normally from external reset generetaor and/or switch |
// output active high global reset sync with two DFFs |
`timescale 1 ns/100 ps |
module vl_sync_rst ( rst_n_i, rst_o, clk); |
73,20 → 73,20
reg [0:1] tmp; |
always @ (posedge clk or negedge rst_n_i) |
if (!rst_n_i) |
tmp <= 2'b11; |
tmp <= 2'b00; |
else |
tmp <= {1'b0,tmp[0]}; |
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o)); |
tmp <= {1'b1,tmp[0]}; |
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o)); |
endmodule |
// vl_pll |
`timescale 1 ps/1 ps |
`timescale 1 ns/100 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
parameter period_time_1 = 20000; |
parameter period_time_2 = 20000; |
parameter lock_delay = 2000000; |
parameter period_time_0 = 20; |
parameter period_time_1 = 20; |
parameter period_time_2 = 20; |
parameter lock_delay = 2000; |
input clk_i, rst_n_i; |
output lock; |
output reg [0:number_of_clk-1] clk_o; |
294,33 → 294,6
else |
direction <= going_full;*/ |
endmodule |
module shreg ( d, q, clk, rst); |
parameter depth = 10; |
input d; |
output q; |
input clk, rst; |
reg [1:depth] dffs; |
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
module shreg_ce ( d, ce, q, clk, rst); |
parameter depth = 10; |
input d, ce; |
output q; |
input clk, rst; |
reg [1:depth] dffs; |
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
if (ce) |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
module delay ( d, q, clk, rst); |
parameter depth = 10; |
input d; |
334,20 → 307,6
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
module delay_emptyflag ( d, q, emptyflag, clk, rst); |
parameter depth = 10; |
input d; |
output q, emptyflag; |
input clk, rst; |
reg [1:depth] dffs; |
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
assign emptyflag = !(|dffs); |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
1951,41 → 1910,3
.b_rst(wbm_rst) |
); |
endmodule |
// WB ROM |
module wb_boot_rom ( |
wb_adr_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_ack_o, wb_clk, wb_rst); |
`ifndef BOOT_ROM |
`define BOOT_ROM "boot_rom.v" |
`endif |
parameter addr_width = 5; |
input [(addr_width+2)-1:2] wb_adr_i; |
input wb_stb_i; |
input wb_cyc_i; |
output reg [31:0] wb_dat_o; |
output reg wb_ack_o; |
input wb_clk; |
input wb_rst; |
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_dat_o <= 32'h15000000; |
else |
case (wb_adr_i) |
`include `BOOT_ROM |
/* |
// Zero r0 and jump to 0x00000100 |
0 : wb_dat_o <= 32'h18000000; |
1 : wb_dat_o <= 32'hA8200000; |
2 : wb_dat_o <= 32'hA8C00100; |
3 : wb_dat_o <= 32'h44003000; |
4 : wb_dat_o <= 32'h15000000; |
*/ |
default: |
wb_dat_o <= 32'h00000000; |
endcase // case (wb_adr_i) |
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_ack_o <= 1'b0; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; |
endmodule |
/trunk/rtl/verilog/registers.v
287,39 → 287,6
endmodule |
`endif |
|
module shreg ( d, q, clk, rst); |
parameter depth = 10; |
input d; |
output q; |
input clk, rst; |
|
reg [1:depth] dffs; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
|
module shreg_ce ( d, ce, q, clk, rst); |
parameter depth = 10; |
input d, ce; |
output q; |
input clk, rst; |
|
reg [1:depth] dffs; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
if (ce) |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
|
module delay ( d, q, clk, rst); |
parameter depth = 10; |
input d; |
334,21 → 301,4
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
|
module delay_emptyflag ( d, q, emptyflag, clk, rst); |
parameter depth = 10; |
input d; |
output q, emptyflag; |
input clk, rst; |
|
reg [1:depth] dffs; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
assign emptyflag = !(|dffs); |
endmodule |
endmodule |
/trunk/rtl/verilog/versatile_library_altera.v
46,7 → 46,7
// ALTERA |
//ACTEL |
// sync reset |
// input active lo async reset, normally from external reset generator and/or switch |
// input active lo async reset, normally from external reset generetaor and/or switch |
// output active high global reset sync with two DFFs |
`timescale 1 ns/100 ps |
module vl_sync_rst ( rst_n_i, rst_o, clk); |
55,10 → 55,10
reg [0:1] tmp; |
always @ (posedge clk or negedge rst_n_i) |
if (!rst_n_i) |
tmp <= 2'b11; |
tmp <= 2'b00; |
else |
tmp <= {1'b0,tmp[0]}; |
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o)); |
tmp <= {1'b1,tmp[0]}; |
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o)); |
endmodule |
// vl_pll |
//altera |
280,33 → 280,6
input clk; |
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q)); |
endmodule |
module shreg ( d, q, clk, rst); |
parameter depth = 10; |
input d; |
output q; |
input clk, rst; |
reg [1:depth] dffs; |
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
module shreg_ce ( d, ce, q, clk, rst); |
parameter depth = 10; |
input d, ce; |
output q; |
input clk, rst; |
reg [1:depth] dffs; |
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
if (ce) |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
module delay ( d, q, clk, rst); |
parameter depth = 10; |
input d; |
320,20 → 293,6
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
module delay_emptyflag ( d, q, emptyflag, clk, rst); |
parameter depth = 10; |
input d; |
output q, emptyflag; |
input clk, rst; |
reg [1:depth] dffs; |
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
assign emptyflag = !(|dffs); |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
1937,41 → 1896,3
.b_rst(wbm_rst) |
); |
endmodule |
// WB ROM |
module wb_boot_rom ( |
wb_adr_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_ack_o, wb_clk, wb_rst); |
//E2_ifndef BOOT_ROM |
//E2_define BOOT_ROM "boot_rom.v" |
//E2_endif |
parameter addr_width = 5; |
input [(addr_width+2)-1:2] wb_adr_i; |
input wb_stb_i; |
input wb_cyc_i; |
output reg [31:0] wb_dat_o; |
output reg wb_ack_o; |
input wb_clk; |
input wb_rst; |
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_dat_o <= 32'h15000000; |
else |
case (wb_adr_i) |
//E2_include `BOOT_ROM |
/* |
// Zero r0 and jump to 0x00000100 |
0 : wb_dat_o <= 32'h18000000; |
1 : wb_dat_o <= 32'hA8200000; |
2 : wb_dat_o <= 32'hA8C00100; |
3 : wb_dat_o <= 32'h44003000; |
4 : wb_dat_o <= 32'h15000000; |
*/ |
default: |
wb_dat_o <= 32'h00000000; |
endcase // case (wb_adr_i) |
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_ack_o <= 1'b0; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; |
endmodule |
/trunk/rtl/verilog/wb.v
238,49 → 238,3
); |
|
endmodule |
|
// WB ROM |
module wb_boot_rom ( |
wb_adr_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_ack_o, wb_clk, wb_rst); |
|
//E2_ifndef BOOT_ROM |
//E2_define BOOT_ROM "boot_rom.v" |
//E2_endif |
parameter addr_width = 5; |
|
input [(addr_width+2)-1:2] wb_adr_i; |
input wb_stb_i; |
input wb_cyc_i; |
output reg [31:0] wb_dat_o; |
output reg wb_ack_o; |
input wb_clk; |
input wb_rst; |
|
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_dat_o <= 32'h15000000; |
else |
case (wb_adr_i) |
//E2_include `BOOT_ROM |
/* |
// Zero r0 and jump to 0x00000100 |
0 : wb_dat_o <= 32'h18000000; |
1 : wb_dat_o <= 32'hA8200000; |
2 : wb_dat_o <= 32'hA8C00100; |
3 : wb_dat_o <= 32'h44003000; |
4 : wb_dat_o <= 32'h15000000; |
*/ |
default: |
wb_dat_o <= 32'h00000000; |
|
endcase // case (wb_adr_i) |
|
|
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_ack_o <= 1'b0; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; |
|
endmodule |
/trunk/rtl/verilog/clk_and_reset.v
84,7 → 84,7
`endif //ACTEL |
|
// sync reset |
// input active lo async reset, normally from external reset generator and/or switch |
// input active lo async reset, normally from external reset generetaor and/or switch |
// output active high global reset sync with two DFFs |
`timescale 1 ns/100 ps |
module vl_sync_rst ( rst_n_i, rst_o, clk); |
93,22 → 93,22
reg [0:1] tmp; |
always @ (posedge clk or negedge rst_n_i) |
if (!rst_n_i) |
tmp <= 2'b11; |
tmp <= 2'b00; |
else |
tmp <= {1'b0,tmp[0]}; |
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o)); |
tmp <= {1'b1,tmp[0]}; |
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o)); |
endmodule |
|
// vl_pll |
`ifdef ACTEL |
`timescale 1 ps/1 ps |
`timescale 1 ns/100 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
parameter period_time_1 = 20000; |
parameter period_time_2 = 20000; |
parameter lock_delay = 2000000; |
parameter period_time_0 = 20; |
parameter period_time_1 = 20; |
parameter period_time_2 = 20; |
parameter lock_delay = 2000; |
input clk_i, rst_n_i; |
output lock; |
output reg [0:number_of_clk-1] clk_o; |
205,13 → 205,13
`else |
|
// generic PLL |
`timescale 1 ps/1 ps |
`timescale 1 ns/100 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
parameter period_time_1 = 20000; |
parameter period_time_2 = 20000; |
parameter period_time_0 = 20; |
parameter period_time_1 = 20; |
parameter period_time_2 = 20; |
parameter lock_delay = 2000; |
input clk_i, rst_n_i; |
output lock; |
242,4 → 242,4
endmodule |
|
`endif //altera |
`endif //actel |
`endif //actel |
/trunk/doc/src/Versatile_library.odt
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/trunk/doc/Versatile_library.pdf
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