URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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- This comparison shows the changes necessary to convert path
/versatile_library
- from Rev 21 to Rev 22
- ↔ Reverse comparison
Rev 21 → Rev 22
/trunk/rtl/verilog/versatile_library.v
645,7 → 645,7
parameter nr_of_ports = 4; |
input [width-1:0] a3, a2, a1, a0; |
input [nr_of_ports-1:0] sel; |
output reg [width-1:0] dout; |
output [width-1:0] dout; |
|
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
667,7 → 667,7
parameter nr_of_ports = 5; |
input [width-1:0] a4, a3, a2, a1, a0; |
input [nr_of_ports-1:0] sel; |
output reg [width-1:0] dout; |
output [width-1:0] dout; |
|
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
690,7 → 690,7
parameter nr_of_ports = 6; |
input [width-1:0] a5, a4, a3, a2, a1, a0; |
input [nr_of_ports-1:0] sel; |
output reg [width-1:0] dout; |
output [width-1:0] dout; |
|
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
750,6 → 750,143
////////////////////////////////////////////////////////////////////// |
|
// binary counter |
module vl_cnt_bin ( q, rst, clk); |
|
parameter length = 4; |
output [length:1] q; |
input rst; |
input clk; |
|
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
|
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = qi + {{length-1{1'b0}},1'b1}; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
|
assign q = qi; |
|
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
// binary counter |
module vl_cnt_bin_clear ( clear, q, rst, clk); |
|
parameter length = 4; |
input clear; |
output [length:1] q; |
input rst; |
input clk; |
|
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
|
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
|
assign q = qi; |
|
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
// binary counter |
module vl_cnt_bin_ce ( cke, q, rst, clk); |
|
parameter length = 4; |
1287,6 → 1424,130
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
// LFSR counter |
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk); |
|
parameter length = 4; |
input cke; |
output [length:1] q; |
output reg zq; |
input rst; |
input clk; |
|
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
|
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
|
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10000010000000000000; // 0x82000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
|
assign q = qi; |
|
|
always @ (posedge clk or posedge rst) |
if (rst) |
zq <= 1'b1; |
else |
if (cke) |
zq <= q_next == {length{1'b0}}; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
// LFSR counter |
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk); |
/trunk/rtl/verilog/versatile_library_actel.v
394,7 → 394,7
parameter nr_of_ports = 4; |
input [width-1:0] a3, a2, a1, a0; |
input [nr_of_ports-1:0] sel; |
output reg [width-1:0] dout; |
output [width-1:0] dout; |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
410,7 → 410,7
parameter nr_of_ports = 5; |
input [width-1:0] a4, a3, a2, a1, a0; |
input [nr_of_ports-1:0] sel; |
output reg [width-1:0] dout; |
output [width-1:0] dout; |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
427,7 → 427,7
parameter nr_of_ports = 6; |
input [width-1:0] a5, a4, a3, a2, a1, a0; |
input [nr_of_ports-1:0] sel; |
output reg [width-1:0] dout; |
output [width-1:0] dout; |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
482,6 → 482,129
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin ( q, rst, clk); |
parameter length = 4; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_clear ( clear, q, rst, clk); |
parameter length = 4; |
input clear; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce ( cke, q, rst, clk); |
parameter length = 4; |
input cke; |
974,6 → 1097,121
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk); |
parameter length = 4; |
input cke; |
output [length:1] q; |
output reg zq; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10000010000000000000; // 0x82000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
always @ (posedge clk or posedge rst) |
if (rst) |
zq <= 1'b1; |
else |
if (cke) |
zq <= q_next == {length{1'b0}}; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk); |
parameter length = 4; |
input cke; |
/trunk/rtl/verilog/cnt_bin.csv
0,0 → 1,14
Name,type,,,, |
vl_cnt_bin,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,0,0,, |
,,,,, |
q,q_bin,z,zq,level1,level2 |
1,1,0,0,0,0 |
,,,,, |
wrap,wrap_around,,,, |
0,1,,,, |
,,,,, |
length,clear_value,set_value,wrap_value,level1,level2 |
4,0,1,0,15, |
/trunk/rtl/verilog/cnt_bin_clear.csv
0,0 → 1,14
Name,type,,,, |
vl_cnt_bin_clear,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
1,0,0,0,, |
,,,,, |
q,q_bin,z,zq,level1,level2 |
1,1,0,0,0,0 |
,,,,, |
wrap,wrap_around,,,, |
0,1,,,, |
,,,,, |
length,clear_value,set_value,wrap_value,level1,level2 |
4,0,1,0,15, |
/trunk/rtl/verilog/Makefile
2,12 → 2,15
VERILOG_FILES += registers.v |
VERILOG_FILES += logic.v |
|
VERILOG_FILES_CNT = vl_cnt_bin_ce.v |
VERILOG_FILES_CNT = vl_cnt_bin.v |
VERILOG_FILES_CNT += vl_cnt_bin_clear.v |
VERILOG_FILES_CNT += vl_cnt_bin_ce.v |
VERILOG_FILES_CNT += vl_cnt_bin_ce_clear.v |
VERILOG_FILES_CNT += vl_cnt_bin_ce_clear_set_rew.v |
VERILOG_FILES_CNT += vl_cnt_bin_ce_rew_l1.v |
VERILOG_FILES_CNT += vl_cnt_lfsr_zq.v |
VERILOG_FILES_CNT += vl_cnt_lfsr_ce_zq.v |
VERILOG_FILES_CNT += vl_cnt_lfsr_ce_q_zq.v |
VERILOG_FILES_CNT += vl_cnt_lfsr_ce_rew_l1.v |
VERILOG_FILES_CNT += vl_cnt_gray.v |
VERILOG_FILES_CNT += vl_cnt_gray_ce.v |
29,6 → 32,8
|
#.PHONY: $(VERILOG_FILES_CNT) |
$(VERILOG_FILES_CNT): |
./versatile_counter_generator.php cnt_bin.csv > vl_cnt_bin.v |
./versatile_counter_generator.php cnt_bin_clear.csv > vl_cnt_bin_clear.v |
./versatile_counter_generator.php cnt_bin_ce.csv > vl_cnt_bin_ce.v |
./versatile_counter_generator.php cnt_bin_ce_clear.csv > vl_cnt_bin_ce_clear.v |
./versatile_counter_generator.php cnt_bin_ce_clear_set_rew.csv > vl_cnt_bin_ce_clear_set_rew.v |
35,6 → 40,7
./versatile_counter_generator.php cnt_bin_ce_rew_l1.csv > vl_cnt_bin_ce_rew_l1.v |
./versatile_counter_generator.php cnt_lfsr_zq.csv > vl_cnt_lfsr_zq.v |
./versatile_counter_generator.php cnt_lfsr_ce_zq.csv > vl_cnt_lfsr_ce_zq.v |
./versatile_counter_generator.php cnt_lfsr_ce_q_zq.csv > vl_cnt_lfsr_ce_q_zq.v |
./versatile_counter_generator.php cnt_lfsr_ce_rew_l1.csv > vl_cnt_lfsr_ce_rew_l1.v |
./versatile_counter_generator.php cnt_gray.csv > vl_cnt_gray.v |
./versatile_counter_generator.php cnt_gray_ce.csv > vl_cnt_gray_ce.v |
/trunk/rtl/verilog/versatile_library_altera.v
380,7 → 380,7
parameter nr_of_ports = 4; |
input [width-1:0] a3, a2, a1, a0; |
input [nr_of_ports-1:0] sel; |
output reg [width-1:0] dout; |
output [width-1:0] dout; |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
396,7 → 396,7
parameter nr_of_ports = 5; |
input [width-1:0] a4, a3, a2, a1, a0; |
input [nr_of_ports-1:0] sel; |
output reg [width-1:0] dout; |
output [width-1:0] dout; |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
413,7 → 413,7
parameter nr_of_ports = 6; |
input [width-1:0] a5, a4, a3, a2, a1, a0; |
input [nr_of_ports-1:0] sel; |
output reg [width-1:0] dout; |
output [width-1:0] dout; |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
468,6 → 468,129
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin ( q, rst, clk); |
parameter length = 4; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_clear ( clear, q, rst, clk); |
parameter length = 4; |
input clear; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce ( cke, q, rst, clk); |
parameter length = 4; |
input cke; |
960,6 → 1083,121
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk); |
parameter length = 4; |
input cke; |
output [length:1] q; |
output reg zq; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10000010000000000000; // 0x82000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
always @ (posedge clk or posedge rst) |
if (rst) |
zq <= 1'b1; |
else |
if (cke) |
zq <= q_next == {length{1'b0}}; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk); |
parameter length = 4; |
input cke; |