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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library
    from Rev 26 to Rev 25
    Reverse comparison

Rev 26 → Rev 25

/trunk/rtl/verilog/memories.v
310,7 → 310,7
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
 
vl_cnt_bin_ce_rew_zq_l1
# (.length(addr_width+1), .level1_value(1<<add_width))
# (.length(addr_width+1), .level1(1<<add_width))
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
 
endmodule
/trunk/rtl/verilog/Makefile
12,8 → 12,6
VERILOG_FILES_CNT += vl_cnt_bin_ce_rew_q_zq_l1.v
VERILOG_FILES_CNT += vl_cnt_lfsr_zq.v
VERILOG_FILES_CNT += vl_cnt_lfsr_ce_zq.v
VERILOG_FILES_CNT += vl_cnt_lfsr_ce_q.v
VERILOG_FILES_CNT += vl_cnt_lfsr_ce_clear_q.v
VERILOG_FILES_CNT += vl_cnt_lfsr_ce_q_zq.v
VERILOG_FILES_CNT += vl_cnt_lfsr_ce_rew_l1.v
VERILOG_FILES_CNT += vl_cnt_gray.v
46,8 → 44,6
./versatile_counter_generator.php cnt_bin_ce_rew_q_zq_l1.csv > vl_cnt_bin_ce_rew_q_zq_l1.v
./versatile_counter_generator.php cnt_lfsr_zq.csv > vl_cnt_lfsr_zq.v
./versatile_counter_generator.php cnt_lfsr_ce_zq.csv > vl_cnt_lfsr_ce_zq.v
./versatile_counter_generator.php cnt_lfsr_ce_q.csv > vl_cnt_lfsr_ce_q.v
./versatile_counter_generator.php cnt_lfsr_ce_clear_q.csv > vl_cnt_lfsr_ce_clear_q.v
./versatile_counter_generator.php cnt_lfsr_ce_q_zq.csv > vl_cnt_lfsr_ce_q_zq.v
./versatile_counter_generator.php cnt_lfsr_ce_rew_l1.csv > vl_cnt_lfsr_ce_rew_l1.v
./versatile_counter_generator.php cnt_gray.csv > vl_cnt_gray.v

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