OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /versatile_library
    from Rev 35 to Rev 34
    ↔ Reverse comparison
  •

Rev 35 → Rev 34

/trunk/rtl/verilog/versatile_library.v
847,7 → 847,7
module vl_mux2_andor ( a1, a0, sel, dout);
 
parameter width = 32;
localparam nr_of_ports = 2;
parameter nr_of_ports = 2;
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
867,7 → 867,7
module vl_mux3_andor ( a2, a1, a0, sel, dout);
 
parameter width = 32;
localparam nr_of_ports = 3;
parameter nr_of_ports = 3;
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
888,7 → 888,7
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
 
parameter width = 32;
localparam nr_of_ports = 4;
parameter nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
910,7 → 910,7
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
 
parameter width = 32;
localparam nr_of_ports = 5;
parameter nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
933,7 → 933,7
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
 
parameter width = 32;
localparam nr_of_ports = 6;
parameter nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
/trunk/rtl/verilog/versatile_library_actel.v
439,7 → 439,7
//////////////////////////////////////////////////////////////////////
module vl_mux2_andor ( a1, a0, sel, dout);
parameter width = 32;
localparam nr_of_ports = 2;
parameter nr_of_ports = 2;
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
453,7 → 453,7
endmodule
module vl_mux3_andor ( a2, a1, a0, sel, dout);
parameter width = 32;
localparam nr_of_ports = 3;
parameter nr_of_ports = 3;
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
468,7 → 468,7
endmodule
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
parameter width = 32;
localparam nr_of_ports = 4;
parameter nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
484,7 → 484,7
endmodule
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
localparam nr_of_ports = 5;
parameter nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
501,7 → 501,7
endmodule
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
localparam nr_of_ports = 6;
parameter nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
/trunk/rtl/verilog/versatile_library_altera.v
547,7 → 547,7
//////////////////////////////////////////////////////////////////////
module vl_mux2_andor ( a1, a0, sel, dout);
parameter width = 32;
localparam nr_of_ports = 2;
parameter nr_of_ports = 2;
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
561,7 → 561,7
endmodule
module vl_mux3_andor ( a2, a1, a0, sel, dout);
parameter width = 32;
localparam nr_of_ports = 3;
parameter nr_of_ports = 3;
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
576,7 → 576,7
endmodule
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
parameter width = 32;
localparam nr_of_ports = 4;
parameter nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
592,7 → 592,7
endmodule
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
localparam nr_of_ports = 5;
parameter nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
609,7 → 609,7
endmodule
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
localparam nr_of_ports = 6;
parameter nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
/trunk/rtl/verilog/logic.v
42,7 → 42,7
module vl_mux2_andor ( a1, a0, sel, dout);
 
parameter width = 32;
localparam nr_of_ports = 2;
parameter nr_of_ports = 2;
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
62,7 → 62,7
module vl_mux3_andor ( a2, a1, a0, sel, dout);
 
parameter width = 32;
localparam nr_of_ports = 3;
parameter nr_of_ports = 3;
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
83,7 → 83,7
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
 
parameter width = 32;
localparam nr_of_ports = 4;
parameter nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
105,7 → 105,7
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
 
parameter width = 32;
localparam nr_of_ports = 5;
parameter nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
128,7 → 128,7
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
 
parameter width = 32;
localparam nr_of_ports = 6;
parameter nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.