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    /versatile_library
    from Rev 38 to Rev 37
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Rev 38 → Rev 37

/trunk/rtl/verilog/versatile_library.v
853,14 → 853,11
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
 
integer i,j;
 
always @ (a, sel)
begin
dout = a[width-1:0] & {width{sel[0]}};
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
for (j=0;j<32;j=j+1)
dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
end
 
endmodule
874,9 → 871,19
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
 
// or
assign dout = tmp[1] | tmp[0];
*/
endmodule
 
module vl_mux3_andor ( a2, a1, a0, sel, dout);
888,9 → 895,21
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
/*
 
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
 
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
*/
endmodule
 
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
902,9 → 921,21
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
 
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
 
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
916,9 → 947,22
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
 
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
 
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
930,9 → 974,23
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
assign tmp[5] = {width{sel[5]}} & a5;
 
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
/trunk/rtl/verilog/versatile_library_actel.v
443,13 → 443,11
input [nr_of_ports*width-1:0] a;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
integer i,j;
always @ (a, sel)
begin
dout = a[width-1:0] & {width{sel[0]}};
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
for (j=0;j<32;j=j+1)
dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
end
endmodule
module vl_mux2_andor ( a1, a0, sel, dout);
459,8 → 457,17
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
// or
assign dout = tmp[1] | tmp[0];
*/
endmodule
module vl_mux3_andor ( a2, a1, a0, sel, dout);
parameter width = 32;
469,8 → 476,18
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
parameter width = 32;
479,8 → 496,19
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
489,8 → 517,20
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
499,8 → 539,21
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
assign tmp[5] = {width{sel[5]}} & a5;
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
/trunk/rtl/verilog/versatile_library_altera.v
551,13 → 551,11
input [nr_of_ports*width-1:0] a;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
integer i,j;
always @ (a, sel)
begin
dout = a[width-1:0] & {width{sel[0]}};
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
for (j=0;j<32;j=j+1)
dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
end
endmodule
module vl_mux2_andor ( a1, a0, sel, dout);
567,8 → 565,17
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
// or
assign dout = tmp[1] | tmp[0];
*/
endmodule
module vl_mux3_andor ( a2, a1, a0, sel, dout);
parameter width = 32;
577,8 → 584,18
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
parameter width = 32;
587,8 → 604,19
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
597,8 → 625,20
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
607,8 → 647,21
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
assign tmp[5] = {width{sel[5]}} & a5;
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
/trunk/rtl/verilog/logic.v
48,14 → 48,11
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
 
integer i,j;
 
always @ (a, sel)
begin
dout = a[width-1:0] & {width{sel[0]}};
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
for (j=0;j<32;j=j+1)
dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
end
 
endmodule
69,9 → 66,19
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
 
// or
assign dout = tmp[1] | tmp[0];
*/
endmodule
 
module vl_mux3_andor ( a2, a1, a0, sel, dout);
83,9 → 90,21
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
/*
 
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
 
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
*/
endmodule
 
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
97,9 → 116,21
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
 
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
 
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
111,9 → 142,22
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
 
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
 
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
125,7 → 169,21
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports))
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
assign tmp[5] = {width{sel[5]}} & a5;
 
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule

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