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Rev 6 → Rev 7

/trunk/rtl/verilog/memories.v
42,8 → 42,26
 
/// ROM
 
module vl_rom ( a, q, clk);
module vl_rom_init ( adr, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(addr_width-1):0] adr;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] rom [(1<<addr_width)-1:0];
parameter memory_file = "vl_rom.vmem";
initial
begin
$readmemh(memory_file, rom);
end
always @ (posedge clk)
q <= rom[adr];
 
endmodule
 
module vl_rom ( adr, q, clk);
 
parameter data_width = 32;
parameter addr_width = 4;
 
65,12 → 83,12
{32'h15000000},
{32'h15000000}};
 
input [addr_width-1:0] a;
input [addr_width-1:0] adr;
output reg [data_width-1:0] q;
input clk;
 
always @ (posedge clk)
q <= data[a];
q <= data[adr];
 
endmodule
 
82,9 → 100,19
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input we;
output reg [(data_width-1):0] q;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk)
begin
if (we)
94,6 → 122,42
 
endmodule
 
module vl_ram_be ( d, adr, be, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
input we;
output reg [(data_width-1):0] q;
input clk;
 
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
genvar i;
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
always @ (posedge clk)
if (we & be[i])
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
end
endgenerate
 
always @ (posedge clk)
q <= ram[adr];
 
endmodule
 
 
// Dual port RAM
 
// ACTEL FPGA should not use logic to handle rw collision
103,7 → 167,7
`define SYN
`endif
 
module vl_dual_port_ram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
114,6 → 178,17
input clk_a, clk_b;
reg [(addr_width-1):0] adr_b_reg;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
122,7 → 197,7
assign q_b = ram[adr_b_reg];
endmodule
 
module vl_dual_port_ram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
134,6 → 209,17
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
144,7 → 230,7
q_b <= ram[adr_b];
endmodule
 
module vl_dual_port_ram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, d_b, we_b, clk_b );
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
158,6 → 244,17
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
292,15 → 389,15
q, rd, fifo_empty, rd_clk, rd_rst
);
 
adr_gen
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
adr_gen
cnt_gray_ce_bin
# (.length(addr_width))
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
 
vl_dual_port_ram_1r1w
vl_dpram_1r1w
# (.data_width(data_width), .addr_width(addr_width))
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
 
310,7 → 407,7
 
endmodule
 
module vl_fifo_2r2w (
module vl_fifo_2r2w_async (
// a side
a_d, a_wr, a_fifo_full,
a_q, a_rd, a_fifo_empty,
358,7 → 455,7
endmodule
 
module vl_fifo_2r2w_simplex (
module vl_fifo_2r2w_async_simplex (
// a side
a_d, a_wr, a_fifo_full,
a_q, a_rd, a_fifo_empty,
398,19 → 495,19
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
adr_gen
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
adr_gen
cnt_gray_ce_bin
# (.length(addr_width))
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
 
adr_gen
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
adr_gen
cnt_gray_ce_bin
# (.length(addr_width))
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
 
418,7 → 515,7
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
 
vfifo_dual_port_ram_dc_dw
vl_dp_ram_2r2w
# (.data_width(data_width), .addr_width(addr_width+1))
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
427,7 → 524,7
# (.addr_width(addr_width))
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
 
versatile_fifo_async_cmp
vl_fifo_async_cmp
# (.addr_width(addr_width))
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
 
/trunk/rtl/verilog/versatile_library.v
1603,8 → 1603,26
 
/// ROM
 
module vl_rom ( a, q, clk);
module vl_rom_init ( adr, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(addr_width-1):0] adr;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] rom [(1<<addr_width)-1:0];
parameter memory_file = "vl_rom.vmem";
initial
begin
$readmemh(memory_file, rom);
end
always @ (posedge clk)
q <= rom[adr];
 
endmodule
 
module vl_rom ( adr, q, clk);
 
parameter data_width = 32;
parameter addr_width = 4;
 
1626,12 → 1644,12
{32'h15000000},
{32'h15000000}};
 
input [addr_width-1:0] a;
input [addr_width-1:0] adr;
output reg [data_width-1:0] q;
input clk;
 
always @ (posedge clk)
q <= data[a];
q <= data[adr];
 
endmodule
 
1643,9 → 1661,19
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input we;
output reg [(data_width-1):0] q;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk)
begin
if (we)
1655,6 → 1683,42
 
endmodule
 
module vl_ram_be ( d, adr, be, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
input we;
output reg [(data_width-1):0] q;
input clk;
 
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
genvar i;
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
always @ (posedge clk)
if (we & be[i])
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
end
endgenerate
 
always @ (posedge clk)
q <= ram[adr];
 
endmodule
 
 
// Dual port RAM
 
// ACTEL FPGA should not use logic to handle rw collision
1664,7 → 1728,7
`define SYN
`endif
 
module vl_dual_port_ram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1675,6 → 1739,17
input clk_a, clk_b;
reg [(addr_width-1):0] adr_b_reg;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
1683,7 → 1758,7
assign q_b = ram[adr_b_reg];
endmodule
 
module vl_dual_port_ram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1695,6 → 1770,17
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
1705,7 → 1791,7
q_b <= ram[adr_b];
endmodule
 
module vl_dual_port_ram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, d_b, we_b, clk_b );
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1719,6 → 1805,17
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
1853,15 → 1950,15
q, rd, fifo_empty, rd_clk, rd_rst
);
 
adr_gen
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
adr_gen
cnt_gray_ce_bin
# (.length(addr_width))
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
 
vl_dual_port_ram_1r1w
vl_dpram_1r1w
# (.data_width(data_width), .addr_width(addr_width))
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
 
1959,19 → 2056,19
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
adr_gen
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
adr_gen
cnt_gray_ce_bin
# (.length(addr_width))
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
 
adr_gen
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
adr_gen
cnt_gray_ce_bin
# (.length(addr_width))
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
 
1979,7 → 2076,7
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
 
vfifo_dual_port_ram_dc_dw
vl_dp_ram_2r2w
# (.data_width(data_width), .addr_width(addr_width+1))
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1988,7 → 2085,7
# (.addr_width(addr_width))
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
 
versatile_fifo_async_cmp
vl_fifo_async_cmp
# (.addr_width(addr_width))
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
 
/trunk/rtl/verilog/versatile_library_actel.v
1277,7 → 1277,22
//// ////
//////////////////////////////////////////////////////////////////////
/// ROM
module vl_rom ( a, q, clk);
module vl_rom_init ( adr, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(addr_width-1):0] adr;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] rom [(1<<addr_width)-1:0];
parameter memory_file = "vl_rom.vmem";
initial
begin
$readmemh(memory_file, rom);
end
always @ (posedge clk)
q <= rom[adr];
endmodule
module vl_rom ( adr, q, clk);
parameter data_width = 32;
parameter addr_width = 4;
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1297,11 → 1312,11
{32'h15000000},
{32'h15000000},
{32'h15000000}};
input [addr_width-1:0] a;
input [addr_width-1:0] adr;
output reg [data_width-1:0] q;
input clk;
always @ (posedge clk)
q <= data[a];
q <= data[adr];
endmodule
// Single port RAM
module vl_ram ( d, adr, we, q, clk);
1310,9 → 1325,18
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input we;
output reg [(data_width-1):0] q;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk)
begin
if (we)
1320,9 → 1344,38
q <= ram[adr];
end
endmodule
module vl_ram_be ( d, adr, be, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
input we;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
genvar i;
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
always @ (posedge clk)
if (we & be[i])
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
end
endgenerate
always @ (posedge clk)
q <= ram[adr];
endmodule
// Dual port RAM
// ACTEL FPGA should not use logic to handle rw collision
module vl_dual_port_ram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1333,6 → 1386,15
input clk_a, clk_b;
reg [(addr_width-1):0] adr_b_reg;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
1340,7 → 1402,7
adr_b_reg <= adr_b;
assign q_b = ram[adr_b_reg];
endmodule
module vl_dual_port_ram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1352,6 → 1414,15
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
1361,7 → 1432,7
always @ (posedge clk_b)
q_b <= ram[adr_b];
endmodule
module vl_dual_port_ram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, d_b, we_b, clk_b );
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1375,6 → 1446,15
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
1472,13 → 1552,13
d, wr, fifo_full, wr_clk, wr_rst,
q, rd, fifo_empty, rd_clk, rd_rst
);
adr_gen
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
adr_gen
cnt_gray_ce_bin
# (.length(addr_width))
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
vl_dual_port_ram_1r1w
vl_dpram_1r1w
# (.data_width(data_width), .addr_width(addr_width))
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
vl_fifo_cmp_async
1561,22 → 1641,22
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
adr_gen
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
adr_gen
cnt_gray_ce_bin
# (.length(addr_width))
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
adr_gen
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
adr_gen
cnt_gray_ce_bin
# (.length(addr_width))
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
vfifo_dual_port_ram_dc_dw
vl_dp_ram_2r2w
# (.data_width(data_width), .addr_width(addr_width+1))
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1583,7 → 1663,7
vl_fifo_async_cmp
# (.addr_width(addr_width))
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
versatile_fifo_async_cmp
vl_fifo_async_cmp
# (.addr_width(addr_width))
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
endmodule
/trunk/rtl/verilog/versatile_library_altera.v
1263,7 → 1263,22
//// ////
//////////////////////////////////////////////////////////////////////
/// ROM
module vl_rom ( a, q, clk);
module vl_rom_init ( adr, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(addr_width-1):0] adr;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] rom [(1<<addr_width)-1:0];
parameter memory_file = "vl_rom.vmem";
initial
begin
$readmemh(memory_file, rom);
end
always @ (posedge clk)
q <= rom[adr];
endmodule
module vl_rom ( adr, q, clk);
parameter data_width = 32;
parameter addr_width = 4;
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1283,11 → 1298,11
{32'h15000000},
{32'h15000000},
{32'h15000000}};
input [addr_width-1:0] a;
input [addr_width-1:0] adr;
output reg [data_width-1:0] q;
input clk;
always @ (posedge clk)
q <= data[a];
q <= data[adr];
endmodule
// Single port RAM
module vl_ram ( d, adr, we, q, clk);
1296,9 → 1311,18
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input we;
output reg [(data_width-1):0] q;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk)
begin
if (we)
1306,9 → 1330,38
q <= ram[adr];
end
endmodule
module vl_ram_be ( d, adr, be, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
input we;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
genvar i;
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
always @ (posedge clk)
if (we & be[i])
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
end
endgenerate
always @ (posedge clk)
q <= ram[adr];
endmodule
// Dual port RAM
// ACTEL FPGA should not use logic to handle rw collision
module vl_dual_port_ram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1319,6 → 1372,15
input clk_a, clk_b;
reg [(addr_width-1):0] adr_b_reg;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
1326,7 → 1388,7
adr_b_reg <= adr_b;
assign q_b = ram[adr_b_reg];
endmodule
module vl_dual_port_ram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1338,6 → 1400,15
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
1347,7 → 1418,7
always @ (posedge clk_b)
q_b <= ram[adr_b];
endmodule
module vl_dual_port_ram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, d_b, we_b, clk_b );
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1361,6 → 1432,15
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
1458,13 → 1538,13
d, wr, fifo_full, wr_clk, wr_rst,
q, rd, fifo_empty, rd_clk, rd_rst
);
adr_gen
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
adr_gen
cnt_gray_ce_bin
# (.length(addr_width))
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
vl_dual_port_ram_1r1w
vl_dpram_1r1w
# (.data_width(data_width), .addr_width(addr_width))
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
vl_fifo_cmp_async
1547,22 → 1627,22
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
adr_gen
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
adr_gen
cnt_gray_ce_bin
# (.length(addr_width))
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
adr_gen
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
adr_gen
cnt_gray_ce_bin
# (.length(addr_width))
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
vfifo_dual_port_ram_dc_dw
vl_dp_ram_2r2w
# (.data_width(data_width), .addr_width(addr_width+1))
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1569,7 → 1649,7
vl_fifo_async_cmp
# (.addr_width(addr_width))
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
versatile_fifo_async_cmp
vl_fifo_async_cmp
# (.addr_width(addr_width))
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
endmodule

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