OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library
    from Rev 61 to Rev 62
    Reverse comparison

Rev 61 → Rev 62

/trunk/rtl/verilog/versatile_library.v
97,6 → 97,15
`endif
`endif
 
`ifdef WB_B3_RAM_BE
`ifndef WB3_ARBITER_TYPE1
`define WB3_ARBITER_TYPE1
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
234,15 → 243,7
`define DPRAM_1R1W
`endif
`endif
 
`ifdef WB_B3_RAM_BE
`ifndef WB3_ARBITER_TYPE1
`define WB3_ARBITER_TYPE1
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile library, clock and reset ////
//// ////
/trunk/rtl/verilog/defines.v
97,6 → 97,15
`endif
`endif
 
`ifdef WB_B3_RAM_BE
`ifndef WB3_ARBITER_TYPE1
`define WB3_ARBITER_TYPE1
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
234,12 → 243,3
`define DPRAM_1R1W
`endif
`endif
 
`ifdef WB_B3_RAM_BE
`ifndef WB3_ARBITER_TYPE1
`define WB3_ARBITER_TYPE1
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif

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