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    from Rev 117 to Rev 118
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Rev 117 → Rev 118

/versatile_library/trunk/rtl/verilog/versatile_library.v
3977,9 → 3977,8
input [(addr_width-1):0] adr_a;
input [(addr_width-1):0] adr_b;
input we_a;
output [(data_width-1):0] q_b;
output reg [(data_width-1):0] q_b;
input clk_a, clk_b;
reg [(addr_width-1):0] adr_b_reg;
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
 
parameter memory_init = 0;
4010,9 → 4009,9
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
 
always @ (posedge clk_b)
adr_b_reg <= adr_b;
assign q_b = ram[adr_b_reg];
q_b = ram[adr_b];
endmodule
`endif
4033,7 → 4032,7
output reg [(data_width-1):0] q_a;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
 
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
1417,9 → 1417,8
input [(addr_width-1):0] adr_a;
input [(addr_width-1):0] adr_b;
input we_a;
output [(data_width-1):0] q_b;
output reg [(data_width-1):0] q_b;
input clk_a, clk_b;
reg [(addr_width-1):0] adr_b_reg;
reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
1446,8 → 1445,7
if (we_a)
ram[adr_a] <= d_a;
always @ (posedge clk_b)
adr_b_reg <= adr_b;
assign q_b = ram[adr_b_reg];
q_b = ram[adr_b];
endmodule
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
1461,7 → 1459,7
output reg [(data_width-1):0] q_a;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_szie-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
parameter debug = 0;
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
1524,9 → 1524,8
input [(addr_width-1):0] adr_a;
input [(addr_width-1):0] adr_b;
input we_a;
output [(data_width-1):0] q_b;
output reg [(data_width-1):0] q_b;
input clk_a, clk_b;
reg [(addr_width-1):0] adr_b_reg;
reg [data_width-1:0] ram [mem_size-1:0] ;
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
1553,8 → 1552,7
if (we_a)
ram[adr_a] <= d_a;
always @ (posedge clk_b)
adr_b_reg <= adr_b;
assign q_b = ram[adr_b_reg];
q_b = ram[adr_b];
endmodule
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
1568,7 → 1566,7
output reg [(data_width-1):0] q_a;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_szie-1:0] ;
reg [data_width-1:0] ram [mem_size-1:0] ;
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
parameter debug = 0;
/versatile_library/trunk/rtl/verilog/memories.v
214,9 → 214,8
input [(addr_width-1):0] adr_a;
input [(addr_width-1):0] adr_b;
input we_a;
output [(data_width-1):0] q_b;
output reg [(data_width-1):0] q_b;
input clk_a, clk_b;
reg [(addr_width-1):0] adr_b_reg;
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
 
parameter memory_init = 0;
247,9 → 246,9
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
 
always @ (posedge clk_b)
adr_b_reg <= adr_b;
assign q_b = ram[adr_b_reg];
q_b = ram[adr_b];
endmodule
`endif
270,7 → 269,7
output reg [(data_width-1):0] q_a;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
 
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";

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