URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
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Rev 139 → Rev 140
/versatile_library/trunk/rtl/verilog/versatile_library.v
26,8 → 26,11
`define MULTS |
`define MULTS18X18 |
`define MULT |
`define ARITH_UNIT |
`define SHIFT_UNIT_32 |
`define LOGIC_UNIT |
`define COUNT_UNIT |
`define EXT_UNIT |
|
`define CNT_SHREG_WRAP |
`define CNT_SHREG_CE_WRAP |
777,36 → 780,47
`undef MODULE |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
parameter period_time_1 = 20000; |
parameter period_time_2 = 20000; |
parameter lock_delay = 2000; |
parameter period_time = 20000; |
parameter clk0_mult_by = 1; |
parameter clk0_div_by = 1; |
parameter clk1_mult_by = 1; |
parameter clk1_div_by = 1; |
parameter clk2_mult_by = 1; |
parameter clk3_div_by = 1; |
parameter clk3_mult_by = 1; |
parameter clk3_div_by = 1; |
parameter clk4_mult_by = 1; |
parameter clk4_div_by = 1; |
input clk_i, rst_n_i; |
output lock; |
output reg [0:number_of_clk-1] clk_o; |
output [0:number_of_clk-1] rst_o; |
|
initial |
clk_o = {number_of_clk{1'b0}}; |
|
always |
#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0]; |
#((period_time*clk0_div_by/clk0_mult_by)/2) clk_o[0] <= (!rst_n_i) ? 1'b0 : ~clk_o[0]; |
|
generate if (number_of_clk > 1) |
always |
#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1]; |
#((period_time*clk1_div_by/clk1_mult_by)/2) clk_o[1] <= (!rst_n_i) ? 1'b0 : ~clk_o[1]; |
endgenerate |
|
generate if (number_of_clk > 2) |
always |
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2]; |
#((period_time*clk2_div_by/clk2_mult_by)/2) clk_o[2] <= (!rst_n_i) ? 1'b0 : ~clk_o[2]; |
endgenerate |
|
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
`define MODULE sync_rst |
`BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
`undef MODULE |
end |
generate if (number_of_clk > 3) |
always |
#((period_time*clk3_div_by/clk3_mult_by)/2) clk_o[3] <= (!rst_n_i) ? 1'b0 : ~clk_o[3]; |
endgenerate |
|
generate if (number_of_clk > 4) |
always |
#((period_time*clk4_div_by/clk4_mult_by)/2) clk_o[4] <= (!rst_n_i) ? 1'b0 : ~clk_o[4]; |
endgenerate |
|
assign #lock_delay lock = rst_n_i; |
|
endmodule |
1683,6 → 1697,7
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst); |
`undef MODULE |
parameter width = 1; |
parameter reset_value = 1'b0; |
input [width-1:0] d_o; |
output reg [width-1:0] d_i; |
input oe; |
1702,12 → 1717,12
oe_q[i] <= oe_d[i]; |
always @ (posedge clk or posedge rst) |
if (rst) |
d_o_q[i] <= 1'b0; |
d_o_q[i] <= reset_value; |
else |
d_o_q[i] <= d_o[i]; |
always @ (posedge clk or posedge rst) |
if (rst) |
d_i[i] <= 1'b0; |
d_i[i] <= reset_value; |
else |
d_i[i] <= io_pad[i]; |
assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz; |
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
679,6 → 679,7
`timescale 1ns/1ns |
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst); |
parameter width = 1; |
parameter reset_value = 1'b0; |
input [width-1:0] d_o; |
output reg [width-1:0] d_i; |
input oe; |
698,12 → 699,12
oe_q[i] <= oe_d[i]; |
always @ (posedge clk or posedge rst) |
if (rst) |
d_o_q[i] <= 1'b0; |
d_o_q[i] <= reset_value; |
else |
d_o_q[i] <= d_o[i]; |
always @ (posedge clk or posedge rst) |
if (rst) |
d_i[i] <= 1'b0; |
d_i[i] <= reset_value; |
else |
d_i[i] <= io_pad[i]; |
assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz; |
5168,3 → 5169,155
(opcode==opcode_xor) ? a ^ b : |
b; |
endmodule |
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl); |
parameter width = 32; |
parameter opcode_add = 1'b0; |
parameter opcode_sub = 1'b1; |
input [width-1:0] a,b; |
input c_in, add_sub, sign; |
output [width-1:0] result; |
output c_out, z, ovfl; |
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))}; |
assign z = (result=={width{1'b0}}); |
assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) | |
(~a[width-1] & ~b[width-1] & result[width-1]); |
endmodule |
module vl_count_unit (din, dout, opcode); |
parameter width = 32; |
input [width-1:0] din; |
output [width-1:0] dout; |
input opcode; |
integer i; |
wire [width/32+4:0] ff1, fl1; |
/* |
always @(din) begin |
ff1 = 0; i = 0; |
while (din[i] == 0 && i < width) begin // complex condition |
ff1 = ff1 + 1; |
i = i + 1; |
end |
end |
always @(din) begin |
fl1 = width; i = width-1; |
while (din[i] == 0 && i >= width) begin // complex condition |
fl1 = fl1 - 1; |
i = i - 1; |
end |
end |
*/ |
generate |
if (width==32) begin |
assign ff1 = din[0] ? 6'd1 : |
din[1] ? 6'd2 : |
din[2] ? 6'd3 : |
din[3] ? 6'd4 : |
din[4] ? 6'd5 : |
din[5] ? 6'd6 : |
din[6] ? 6'd7 : |
din[7] ? 6'd8 : |
din[8] ? 6'd9 : |
din[9] ? 6'd10 : |
din[10] ? 6'd11 : |
din[11] ? 6'd12 : |
din[12] ? 6'd13 : |
din[13] ? 6'd14 : |
din[14] ? 6'd15 : |
din[15] ? 6'd16 : |
din[16] ? 6'd17 : |
din[17] ? 6'd18 : |
din[18] ? 6'd19 : |
din[19] ? 6'd20 : |
din[20] ? 6'd21 : |
din[21] ? 6'd22 : |
din[22] ? 6'd23 : |
din[23] ? 6'd24 : |
din[24] ? 6'd25 : |
din[25] ? 6'd26 : |
din[26] ? 6'd27 : |
din[27] ? 6'd28 : |
din[28] ? 6'd29 : |
din[29] ? 6'd30 : |
din[30] ? 6'd31 : |
din[31] ? 6'd32 : |
6'd0; |
assign fl1 = din[31] ? 6'd32 : |
din[30] ? 6'd31 : |
din[29] ? 6'd30 : |
din[28] ? 6'd29 : |
din[27] ? 6'd28 : |
din[26] ? 6'd27 : |
din[25] ? 6'd26 : |
din[24] ? 6'd25 : |
din[23] ? 6'd24 : |
din[22] ? 6'd23 : |
din[21] ? 6'd22 : |
din[20] ? 6'd21 : |
din[19] ? 6'd20 : |
din[18] ? 6'd19 : |
din[17] ? 6'd18 : |
din[16] ? 6'd17 : |
din[15] ? 6'd16 : |
din[14] ? 6'd15 : |
din[13] ? 6'd14 : |
din[12] ? 6'd13 : |
din[11] ? 6'd12 : |
din[10] ? 6'd11 : |
din[9] ? 6'd10 : |
din[8] ? 6'd9 : |
din[7] ? 6'd8 : |
din[6] ? 6'd7 : |
din[5] ? 6'd6 : |
din[4] ? 6'd5 : |
din[3] ? 6'd4 : |
din[2] ? 6'd3 : |
din[1] ? 6'd2 : |
din[0] ? 6'd1 : |
6'd0; |
assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1}; |
end |
endgenerate |
generate |
if (width==64) begin |
assign ff1 = 7'd0; |
assign fl1 = 7'd0; |
assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1}; |
end |
endgenerate |
endmodule |
module vl_ext_unit ( a, b, F, result, opcode); |
parameter width = 32; |
input [width-1:0] a, b; |
input F; |
output reg [width-1:0] result; |
input [2:0] opcode; |
generate |
if (width==32) begin |
always @ (a or b or F or opcode) |
begin |
case (opcode) |
3'b000: result = {{24{1'b0}},a[7:0]}; |
3'b001: result = {{24{a[7]}},a[7:0]}; |
3'b010: result = {{16{1'b0}},a[7:0]}; |
3'b011: result = {{16{a[15]}},a[15:0]}; |
3'b110: result = (F) ? a : b; |
default: result = {b[15:0],16'h0000}; |
endcase |
end |
end |
endgenerate |
generate |
if (width==64) begin |
always @ (a or b or F or opcode) |
begin |
case (opcode) |
3'b000: result = {{56{1'b0}},a[7:0]}; |
3'b001: result = {{56{a[7]}},a[7:0]}; |
3'b010: result = {{48{1'b0}},a[7:0]}; |
3'b011: result = {{48{a[15]}},a[15:0]}; |
3'b110: result = (F) ? a : b; |
default: result = {32'h00000000,b[15:0],16'h0000}; |
endcase |
end |
end |
endgenerate |
endmodule |
/versatile_library/trunk/rtl/verilog/custom_defines.v
13,7 → 13,7
|
//=comment |
//=comment Generate all modules |
//`define ALL |
`define ALL |
|
|
//=comment System Verilog |
22,114 → 22,117
//=tab Clk and reset |
|
//=comment Global buffer for high fanout signals |
`define GBUF |
`define SYNC_RST |
`define PLL |
//`define GBUF |
//`define SYNC_RST |
//`define PLL |
|
//=tab registers |
`define DFF |
`define DFF_ARRAY |
`define DFF_CE |
`define DFF_CE_CLEAR |
`define DF_CE_SET |
`define SPR |
`define SRP |
`define DFF_SR |
`define LATCH |
`define SHREG |
`define SHREG_CE |
`define DELAY |
`define DELAY_EMPTYFLAG |
`define PULSE2TOGGLE |
`define TOGGLE2PULSE |
`define SYNCHRONIZER |
`define CDC |
//`define DFF |
//`define DFF_ARRAY |
//`define DFF_CE |
//`define DFF_CE_CLEAR |
//`define DF_CE_SET |
//`define SPR |
//`define SRP |
//`define DFF_SR |
//`define LATCH |
//`define SHREG |
//`define SHREG_CE |
//`define DELAY |
//`define DELAY_EMPTYFLAG |
//`define PULSE2TOGGLE |
//`define TOGGLE2PULSE |
//`define SYNCHRONIZER |
//`define CDC |
|
//=tab Logic |
`define MUX_ANDOR |
`define MUX2_ANDOR |
`define MUX3_ANDOR |
`define MUX4_ANDOR |
`define MUX5_ANDOR |
`define MUX6_ANDOR |
`define PARITY |
`define SHIFT_UNIT_32 |
`define LOGIC_UNIT |
//`define MUX_ANDOR |
//`define MUX2_ANDOR |
//`define MUX3_ANDOR |
//`define MUX4_ANDOR |
//`define MUX5_ANDOR |
//`define MUX6_ANDOR |
//`define PARITY |
//`define SHIFT_UNIT_32 |
//`define LOGIC_UNIT |
|
//=tab |
|
//=tab IO |
`define IO_DFF_OE |
`define O_DFF |
`define O_DDR |
`define O_CLK |
//`define IO_DFF_OE |
//`define O_DFF |
//`define O_DDR |
//`define O_CLK |
|
//=tab Counters |
//=comment Binary counters |
`define CNT_BIN |
`define CNT_BIN_CE |
`define CNT_BIN_CLEAR |
`define CNT_BIN_CE_CLEAR |
`define CNT_BIN_CE_CLEAR_L1_L2 |
`define CNT_BIN_CE_CLEAR_SET_REW |
`define CNT_BIN_CE_REW_L1 |
`define CNT_BIN_CE_REW_ZQ_L1 |
`define CNT_BIN_CE_REW_Q_ZQ_L1 |
//`define CNT_BIN |
//`define CNT_BIN_CE |
//`define CNT_BIN_CLEAR |
//`define CNT_BIN_CE_CLEAR |
//`define CNT_BIN_CE_CLEAR_L1_L2 |
//`define CNT_BIN_CE_CLEAR_SET_REW |
//`define CNT_BIN_CE_REW_L1 |
//`define CNT_BIN_CE_REW_ZQ_L1 |
//`define CNT_BIN_CE_REW_Q_ZQ_L1 |
//=comment Gray counters |
`define CNT_GRAY |
`define CNT_GRAY_CE |
`define CNT_GRAY_CE_BIN |
//`define CNT_GRAY |
//`define CNT_GRAY_CE |
//`define CNT_GRAY_CE_BIN |
//=comment LFSR counters |
`define CNT_LFSR_ZQ |
`define CNT_LFSR_CE |
`define CNT_LFSR_CE_CLEAR_Q |
`define CNT_LFSR_CE_Q |
`define CNT_LFSR_CE_ZQ |
`define CNT_LFSR_CE_Q_ZQ |
`define CNT_LFSR_CE_REW_L1 |
//`define CNT_LFSR_ZQ |
//`define CNT_LFSR_CE |
//`define CNT_LFSR_CE_CLEAR_Q |
//`define CNT_LFSR_CE_Q |
//`define CNT_LFSR_CE_ZQ |
//`define CNT_LFSR_CE_Q_ZQ |
//`define CNT_LFSR_CE_REW_L1 |
//=comment Shift register based counters |
`define CNT_SHREG_WRAP |
`define CNT_SHREG_CLEAR |
`define CNT_SHREG_CE_WRAP |
`define CNT_SHREG_CE_CLEAR |
`define CNT_SHREG_CE_CLEAR_WRAP |
//`define CNT_SHREG_WRAP |
//`define CNT_SHREG_CLEAR |
//`define CNT_SHREG_CE_WRAP |
//`define CNT_SHREG_CE_CLEAR |
//`define CNT_SHREG_CE_CLEAR_WRAP |
|
//=tab Memories |
`define ROM_INIT |
`define RAM |
`define RAM_BE |
`define DPRAM_1R1W |
`define DPRAM_2R1W |
`define DPRAM_1R2W |
`define DPRAM_2R2W |
`define DPRAM_BE_2R2W |
`define FIFO_1R1W_FILL_LEVEL_SYNC |
`define FIFO_2R2W_SYNC_SIMPLEX |
`define FIFO_CMP_ASYNC |
`define FIFO_1R1W_ASYNC |
`define FIFO_2R2W_ASYNC |
`define FIFO_2R2W_ASYNC_SIMPLEX |
`define REG_FILE |
//`define ROM_INIT |
//`define RAM |
//`define RAM_BE |
//`define DPRAM_1R1W |
//`define DPRAM_2R1W |
//`define DPRAM_1R2W |
//`define DPRAM_2R2W |
//`define DPRAM_BE_2R2W |
//`define FIFO_1R1W_FILL_LEVEL_SYNC |
//`define FIFO_2R2W_SYNC_SIMPLEX |
//`define FIFO_CMP_ASYNC |
//`define FIFO_1R1W_ASYNC |
//`define FIFO_2R2W_ASYNC |
//`define FIFO_2R2W_ASYNC_SIMPLEX |
//`define REG_FILE |
|
//=tab Wishbone |
`define WB3AVALON_BRIDGE |
`define WB3WB3_BRIDGE |
`define WB3_ARBITER_TYPE1 |
`define WB_ADR_INC |
`define WB_RAM |
`define WB_SHADOW_RAM |
`define WB_B4_ROM |
`define WB_BOOT_ROM |
`define WB_DPRAM |
`define WB_CACHE |
`define WB_AVALON_BRIDGE |
`define WB_AVALON_MEM_CACHE |
`define WB_SDR_SDRAM_CTRL |
//`define WB3AVALON_BRIDGE |
//`define WB3WB3_BRIDGE |
//`define WB3_ARBITER_TYPE1 |
//`define WB_ADR_INC |
//`define WB_RAM |
//`define WB_SHADOW_RAM |
//`define WB_B4_ROM |
//`define WB_BOOT_ROM |
//`define WB_DPRAM |
//`define WB_CACHE |
//`define WB_AVALON_BRIDGE |
//`define WB_AVALON_MEM_CACHE |
//`define WB_SDR_SDRAM_CTRL |
|
//=tab Arithmetic |
`define MULTS |
`define MULTS18X18 |
`define MULT |
//`define MULTS |
//`define MULTS18X18 |
//`define MULT |
//`define ARITH_UNIT |
//`define COUNT_UNIT |
//`define EXT_UNIT |
|
/////////////////////////////////////// |
// dependencies |
407,4 → 410,4
`endif |
|
// size to width |
`define SIZE2WIDTH_EXPR |
//`define SIZE2WIDTH_EXPR |
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
786,6 → 786,7
`timescale 1ns/1ns |
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst); |
parameter width = 1; |
parameter reset_value = 1'b0; |
input [width-1:0] d_o; |
output reg [width-1:0] d_i; |
input oe; |
805,12 → 806,12
oe_q[i] <= oe_d[i]; |
always @ (posedge clk or posedge rst) |
if (rst) |
d_o_q[i] <= 1'b0; |
d_o_q[i] <= reset_value; |
else |
d_o_q[i] <= d_o[i]; |
always @ (posedge clk or posedge rst) |
if (rst) |
d_i[i] <= 1'b0; |
d_i[i] <= reset_value; |
else |
d_i[i] <= io_pad[i]; |
assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz; |
5261,3 → 5262,155
(opcode==opcode_xor) ? a ^ b : |
b; |
endmodule |
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl); |
parameter width = 32; |
parameter opcode_add = 1'b0; |
parameter opcode_sub = 1'b1; |
input [width-1:0] a,b; |
input c_in, add_sub, sign; |
output [width-1:0] result; |
output c_out, z, ovfl; |
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))}; |
assign z = (result=={width{1'b0}}); |
assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) | |
(~a[width-1] & ~b[width-1] & result[width-1]); |
endmodule |
module vl_count_unit (din, dout, opcode); |
parameter width = 32; |
input [width-1:0] din; |
output [width-1:0] dout; |
input opcode; |
integer i; |
wire [width/32+4:0] ff1, fl1; |
/* |
always @(din) begin |
ff1 = 0; i = 0; |
while (din[i] == 0 && i < width) begin // complex condition |
ff1 = ff1 + 1; |
i = i + 1; |
end |
end |
always @(din) begin |
fl1 = width; i = width-1; |
while (din[i] == 0 && i >= width) begin // complex condition |
fl1 = fl1 - 1; |
i = i - 1; |
end |
end |
*/ |
generate |
if (width==32) begin |
assign ff1 = din[0] ? 6'd1 : |
din[1] ? 6'd2 : |
din[2] ? 6'd3 : |
din[3] ? 6'd4 : |
din[4] ? 6'd5 : |
din[5] ? 6'd6 : |
din[6] ? 6'd7 : |
din[7] ? 6'd8 : |
din[8] ? 6'd9 : |
din[9] ? 6'd10 : |
din[10] ? 6'd11 : |
din[11] ? 6'd12 : |
din[12] ? 6'd13 : |
din[13] ? 6'd14 : |
din[14] ? 6'd15 : |
din[15] ? 6'd16 : |
din[16] ? 6'd17 : |
din[17] ? 6'd18 : |
din[18] ? 6'd19 : |
din[19] ? 6'd20 : |
din[20] ? 6'd21 : |
din[21] ? 6'd22 : |
din[22] ? 6'd23 : |
din[23] ? 6'd24 : |
din[24] ? 6'd25 : |
din[25] ? 6'd26 : |
din[26] ? 6'd27 : |
din[27] ? 6'd28 : |
din[28] ? 6'd29 : |
din[29] ? 6'd30 : |
din[30] ? 6'd31 : |
din[31] ? 6'd32 : |
6'd0; |
assign fl1 = din[31] ? 6'd32 : |
din[30] ? 6'd31 : |
din[29] ? 6'd30 : |
din[28] ? 6'd29 : |
din[27] ? 6'd28 : |
din[26] ? 6'd27 : |
din[25] ? 6'd26 : |
din[24] ? 6'd25 : |
din[23] ? 6'd24 : |
din[22] ? 6'd23 : |
din[21] ? 6'd22 : |
din[20] ? 6'd21 : |
din[19] ? 6'd20 : |
din[18] ? 6'd19 : |
din[17] ? 6'd18 : |
din[16] ? 6'd17 : |
din[15] ? 6'd16 : |
din[14] ? 6'd15 : |
din[13] ? 6'd14 : |
din[12] ? 6'd13 : |
din[11] ? 6'd12 : |
din[10] ? 6'd11 : |
din[9] ? 6'd10 : |
din[8] ? 6'd9 : |
din[7] ? 6'd8 : |
din[6] ? 6'd7 : |
din[5] ? 6'd6 : |
din[4] ? 6'd5 : |
din[3] ? 6'd4 : |
din[2] ? 6'd3 : |
din[1] ? 6'd2 : |
din[0] ? 6'd1 : |
6'd0; |
assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1}; |
end |
endgenerate |
generate |
if (width==64) begin |
assign ff1 = 7'd0; |
assign fl1 = 7'd0; |
assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1}; |
end |
endgenerate |
endmodule |
module vl_ext_unit ( a, b, F, result, opcode); |
parameter width = 32; |
input [width-1:0] a, b; |
input F; |
output reg [width-1:0] result; |
input [2:0] opcode; |
generate |
if (width==32) begin |
always @ (a or b or F or opcode) |
begin |
case (opcode) |
3'b000: result = {{24{1'b0}},a[7:0]}; |
3'b001: result = {{24{a[7]}},a[7:0]}; |
3'b010: result = {{16{1'b0}},a[7:0]}; |
3'b011: result = {{16{a[15]}},a[15:0]}; |
3'b110: result = (F) ? a : b; |
default: result = {b[15:0],16'h0000}; |
endcase |
end |
end |
endgenerate |
generate |
if (width==64) begin |
always @ (a or b or F or opcode) |
begin |
case (opcode) |
3'b000: result = {{56{1'b0}},a[7:0]}; |
3'b001: result = {{56{a[7]}},a[7:0]}; |
3'b010: result = {{48{1'b0}},a[7:0]}; |
3'b011: result = {{48{a[15]}},a[15:0]}; |
3'b110: result = (F) ? a : b; |
default: result = {32'h00000000,b[15:0],16'h0000}; |
endcase |
end |
end |
endgenerate |
endmodule |
/versatile_library/trunk/rtl/verilog/defines.v
26,8 → 26,11
`define MULTS |
`define MULTS18X18 |
`define MULT |
`define ARITH_UNIT |
`define SHIFT_UNIT_32 |
`define LOGIC_UNIT |
`define COUNT_UNIT |
`define EXT_UNIT |
|
`define CNT_SHREG_WRAP |
`define CNT_SHREG_CE_WRAP |