URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 147 to Rev 148
- ↔ Reverse comparison
Rev 147 → Rev 148
/versatile_library/trunk/rtl/verilog/versatile_library.v
5044,7 → 5044,7
|
always @ (posedge clk or posedge rst) |
if (rst) |
{sel1, sel2, wreg} <= {1'b0,1'b0,{data_width{1'b0}}}; |
{sel1, sel2, wreg} <= {1'b0,1'b0,{dw{1'b0}}}; |
else |
{sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3}; |
assign rd1 = (sel1) ? wreg : rd1mem; |
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
3437,7 → 3437,7
.clk_b(clk) ); |
always @ (posedge clk or posedge rst) |
if (rst) |
{sel1, sel2, wreg} <= {1'b0,1'b0,{data_width{1'b0}}}; |
{sel1, sel2, wreg} <= {1'b0,1'b0,{dw{1'b0}}}; |
else |
{sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3}; |
assign rd1 = (sel1) ? wreg : rd1mem; |
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
3532,7 → 3532,7
.clk_b(clk) ); |
always @ (posedge clk or posedge rst) |
if (rst) |
{sel1, sel2, wreg} <= {1'b0,1'b0,{data_width{1'b0}}}; |
{sel1, sel2, wreg} <= {1'b0,1'b0,{dw{1'b0}}}; |
else |
{sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3}; |
assign rd1 = (sel1) ? wreg : rd1mem; |
/versatile_library/trunk/rtl/verilog/memories.v
1134,7 → 1134,7
|
always @ (posedge clk or posedge rst) |
if (rst) |
{sel1, sel2, wreg} <= {1'b0,1'b0,{data_width{1'b0}}}; |
{sel1, sel2, wreg} <= {1'b0,1'b0,{dw{1'b0}}}; |
else |
{sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3}; |
assign rd1 = (sel1) ? wreg : rd1mem; |