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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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    from Rev 29 to Rev 30
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Rev 29 → Rev 30

/versatile_library/trunk/rtl/verilog/versatile_library.v
1103,11 → 1103,12
 
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 7;
parameter level1_value = 15;
parameter wrap_value = 15;
parameter level1_value = 8;
parameter level2_value = 15;
 
wire rew;
assign rew=1'b0;
assign rew = 1'b0;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1279,7 → 1280,7
parameter level1_value = 15;
 
wire clear;
assign clear=1'b0;
assign clear = 1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1366,7 → 1367,7
parameter level1_value = 15;
 
wire clear;
assign clear=1'b0;
assign clear = 1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1461,7 → 1462,7
parameter level1_value = 15;
 
wire clear;
assign clear=1'b0;
assign clear = 1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
2153,7 → 2154,7
parameter level1_value = 15;
 
wire clear;
assign clear=1'b0;
assign clear = 1'b0;
reg [length:1] qi;
reg lfsr_fb, lfsr_fb_rew;
wire [length:1] q_next, q_next_fw, q_next_rew;
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
789,10 → 789,11
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 7;
parameter level1_value = 15;
parameter wrap_value = 15;
parameter level1_value = 8;
parameter level2_value = 15;
wire rew;
assign rew=1'b0;
assign rew = 1'b0;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
948,7 → 949,7
parameter wrap_value = 1;
parameter level1_value = 15;
wire clear;
assign clear=1'b0;
assign clear = 1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1027,7 → 1028,7
parameter wrap_value = 1;
parameter level1_value = 15;
wire clear;
assign clear=1'b0;
assign clear = 1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1113,7 → 1114,7
parameter wrap_value = 1;
parameter level1_value = 15;
wire clear;
assign clear=1'b0;
assign clear = 1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1753,7 → 1754,7
parameter wrap_value = 8;
parameter level1_value = 15;
wire clear;
assign clear=1'b0;
assign clear = 1'b0;
reg [length:1] qi;
reg lfsr_fb, lfsr_fb_rew;
wire [length:1] q_next, q_next_fw, q_next_rew;
/versatile_library/trunk/rtl/verilog/cnt_bin_ce_clear_l1_l2.csv
11,4 → 11,4
0,1,,,,
,,,,,
length,clear_value,set_value,wrap_value,level1,level2
4,0,1,7,15,
4,0,1,15,8,15
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
775,10 → 775,11
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 7;
parameter level1_value = 15;
parameter wrap_value = 15;
parameter level1_value = 8;
parameter level2_value = 15;
wire rew;
assign rew=1'b0;
assign rew = 1'b0;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
934,7 → 935,7
parameter wrap_value = 1;
parameter level1_value = 15;
wire clear;
assign clear=1'b0;
assign clear = 1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1013,7 → 1014,7
parameter wrap_value = 1;
parameter level1_value = 15;
wire clear;
assign clear=1'b0;
assign clear = 1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1099,7 → 1100,7
parameter wrap_value = 1;
parameter level1_value = 15;
wire clear;
assign clear=1'b0;
assign clear = 1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1739,7 → 1740,7
parameter wrap_value = 8;
parameter level1_value = 15;
wire clear;
assign clear=1'b0;
assign clear = 1'b0;
reg [length:1] qi;
reg lfsr_fb, lfsr_fb_rew;
wire [length:1] q_next, q_next_fw, q_next_rew;

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