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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
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    from Rev 53 to Rev 54
    Reverse comparison

Rev 53 → Rev 54

/versatile_library/trunk/rtl/verilog/versatile_library.v
4680,7 → 4680,7
if (rst)
wb_ack_o <= 1'b0;
else
wb_ack_o <= wb_stb_i & wb_cyc_i
wb_ack_o <= wb_stb_i & wb_cyc_i;
 
assign wb_stall_o = 1'b0;
 
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
1979,7 → 1979,7
if (rst)
wb_ack_o <= 1'b0;
else
wb_ack_o <= wb_stb_i & wb_cyc_i
wb_ack_o <= wb_stb_i & wb_cyc_i;
assign wb_stall_o = 1'b0;
endmodule
// WB ROM
/versatile_library/trunk/rtl/verilog/wb.v
510,7 → 510,7
if (rst)
wb_ack_o <= 1'b0;
else
wb_ack_o <= wb_stb_i & wb_cyc_i
wb_ack_o <= wb_stb_i & wb_cyc_i;
 
assign wb_stall_o = 1'b0;
 
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
2084,7 → 2084,7
if (rst)
wb_ack_o <= 1'b0;
else
wb_ack_o <= wb_stb_i & wb_cyc_i
wb_ack_o <= wb_stb_i & wb_cyc_i;
assign wb_stall_o = 1'b0;
endmodule
// WB ROM

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