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    from Rev 60 to Rev 61
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Rev 60 → Rev 61

/versatile_library/trunk/rtl/verilog/versatile_library.v
234,7 → 234,15
`define DPRAM_1R1W
`endif
`endif
//////////////////////////////////////////////////////////////////////
 
`ifdef WB_B3_RAM_BE
`ifndef WB3_ARBITER_TYPE1
`define WB3_ARBITER_TYPE1
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile library, clock and reset ////
//// ////
4667,7 → 4675,7
`define MODULE wb_b3_ram_be
module `BASE`MODULE (
`undef MODULE
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
 
parameter nr_of_ports = 3;
4687,6 → 4695,7
input [dw-1:0] wb_dat_i;
input [aw-1:0] wb_adr_i;
input [cw-1:0] wb_cti_i;
input [bw-1:0] wb_bte_i;
input [sw-1:0] wb_sel_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
4701,6 → 4710,7
wire [dat_size-1:0] wbs_dat_i;
wire [adr_size-1:0] wbs_adr_i;
wire [2:0] wbs_cti_i;
wire [1:0] wbs_bte_i;
wire [(dat_size/8)-1:0] wbs_sel_i;
wire wbs_we_i, wbs_stb_i, wbs_cyc_i;
wire [dat_size-1:0] wbs_dat_o;
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
1962,7 → 1962,7
endmodule
// WB RAM with byte enable
module vl_wb_b3_ram_be (
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
parameter nr_of_ports = 3;
parameter wb_arbiter_type = 1;
1979,6 → 1979,7
input [dw-1:0] wb_dat_i;
input [aw-1:0] wb_adr_i;
input [cw-1:0] wb_cti_i;
input [bw-1:0] wb_bte_i;
input [sw-1:0] wb_sel_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
1991,6 → 1992,7
wire [dat_size-1:0] wbs_dat_i;
wire [adr_size-1:0] wbs_adr_i;
wire [2:0] wbs_cti_i;
wire [1:0] wbs_bte_i;
wire [(dat_size/8)-1:0] wbs_sel_i;
wire wbs_we_i, wbs_stb_i, wbs_cyc_i;
wire [dat_size-1:0] wbs_dat_o;
/versatile_library/trunk/rtl/verilog/wb.v
472,7 → 472,7
`define MODULE wb_b3_ram_be
module `BASE`MODULE (
`undef MODULE
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
 
parameter nr_of_ports = 3;
492,6 → 492,7
input [dw-1:0] wb_dat_i;
input [aw-1:0] wb_adr_i;
input [cw-1:0] wb_cti_i;
input [bw-1:0] wb_bte_i;
input [sw-1:0] wb_sel_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
506,6 → 507,7
wire [dat_size-1:0] wbs_dat_i;
wire [adr_size-1:0] wbs_adr_i;
wire [2:0] wbs_cti_i;
wire [1:0] wbs_bte_i;
wire [(dat_size/8)-1:0] wbs_sel_i;
wire wbs_we_i, wbs_stb_i, wbs_cyc_i;
wire [dat_size-1:0] wbs_dat_o;
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
2067,7 → 2067,7
endmodule
// WB RAM with byte enable
module vl_wb_b3_ram_be (
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
parameter nr_of_ports = 3;
parameter wb_arbiter_type = 1;
2084,6 → 2084,7
input [dw-1:0] wb_dat_i;
input [aw-1:0] wb_adr_i;
input [cw-1:0] wb_cti_i;
input [bw-1:0] wb_bte_i;
input [sw-1:0] wb_sel_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
2096,6 → 2097,7
wire [dat_size-1:0] wbs_dat_i;
wire [adr_size-1:0] wbs_adr_i;
wire [2:0] wbs_cti_i;
wire [1:0] wbs_bte_i;
wire [(dat_size/8)-1:0] wbs_sel_i;
wire wbs_we_i, wbs_stb_i, wbs_cyc_i;
wire [dat_size-1:0] wbs_dat_o;
/versatile_library/trunk/rtl/verilog/defines.v
234,3 → 234,12
`define DPRAM_1R1W
`endif
`endif
 
`ifdef WB_B3_RAM_BE
`ifndef WB3_ARBITER_TYPE1
`define WB3_ARBITER_TYPE1
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif

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