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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

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Rev 83 → Rev 84

/versatile_library/trunk/rtl/verilog/wb.v
44,11 → 44,11
// async wb3 - wb3 bridge
`timescale 1ns/1ns
`define MODULE wb_adr_inc
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, ack_o, adr_o, clk, rst);
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
`undef MODULE
parameter adr_width = 10;
parameter max_burst_width = 4;
input cyc_i, stb_i;
input cyc_i, stb_i, we_i;
input [2:0] cti_i;
input [1:0] bte_i;
input [adr_width-1:0] adr_i;
85,7 → 85,9
(cyc_i & !stb_i) ? ws :
cyc;
assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
assign adr_o[max_burst_width-1:0] = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
adr[max_burst_width-1:0];
assign ack_o = last_cycle == cyc;
end
endgenerate
388,6 → 390,8
// avalon master side
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
 
parameter linewrapburst = 1'b0;
 
input [31:0] wbs_dat_i;
input [31:2] wbs_adr_i;
input [3:0] wbs_sel_i;
449,7 → 453,7
end else
if (wbm_we_o) begin
if (!waitrequest & !last_cyc & wbm_cyc_o) begin
counter <= burstcount -1;
counter <= burstcount -4'd1;
end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
counter <= burstcount;
end else if (!waitrequest & wbm_stb_o) begin
799,14 → 803,13
wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
 
parameter adr_size = 16;
parameter adr_lo = 2;
parameter mem_size = 1<<16;
parameter mem_size = 1<<adr_size;
parameter dat_size = 32;
parameter max_burst_width = 4;
parameter memory_init = 1;
parameter memory_file = "vl_ram.vmem";
 
localparam aw = (adr_size - adr_lo);
localparam aw = (adr_size);
localparam dw = dat_size;
localparam sw = dat_size/8;
localparam cw = 3;
821,7 → 824,6
output [dw-1:0] wbs_dat_o;
output wbs_ack_o;
input wb_clk, wb_rst;
reg wbs_ack_o;
 
wire [aw-1:0] adr;
 
837,7 → 839,7
.d(wbs_dat_i),
.adr(adr),
.be(wbs_sel_i),
.we(wbs_we_i),
.we(wbs_we_i & wb_ack_o),
.q(wbs_dat_o),
.clk(wb_clk)
);
849,6 → 851,7
.cti_i(wbs_cti_i),
.bte_i(wbs_bte_i),
.adr_i(wbs_adr_i),
.we_i(wbs_we_i),
.ack_o(wbs_ack_o),
.adr_o(adr),
.clk(wb_clk),
/versatile_library/trunk/rtl/verilog/memories.v
115,10 → 115,12
output reg [(data_width-1):0] q;
input clk;
 
//E2_ifdef SYSTEMVERILOG
logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
//E2_else
reg [data_width-1:0] ram [mem_size-1:0];
reg [data_width-1:0] ram [mem_size-1:0];
wire [data_width/8-1:0] cke;
//E2_endif
 
parameter memory_init = 0;
148,10 → 150,11
 
//E2_else
 
assign cke = {data_width/8{we}} & be;
genvar i;
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
always @ (posedge clk)
if (we & be[i])
if (cke[i])
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
end
endgenerate
161,6 → 164,21
 
//E2_endif
 
// Function to access RAM (for use by Verilator).
function [31:0] get_mem;
// verilator public
input [aw-1:0] addr;
get_mem = ram[addr];
endfunction // get_mem
 
// Function to write RAM (for use by Verilator).
function set_mem;
// verilator public
input [aw-1:0] addr;
input [dw-1:0] data;
ram[addr] = data;
endfunction // set_mem
 
endmodule
`endif
 

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