URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl/verilog
- from Rev 127 to Rev 128
- ↔ Reverse comparison
Rev 127 → Rev 128
/versatile_library.v
4350,9 → 4350,9
if (a_data_width==32 & b_data_width==16) begin : dpram_3216 |
logic [31:0] temp; |
`define MODULE dpram_be_2r2w |
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
`BASE`MODULE # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
`undef MODULE |
dpram6464 ( |
dpram3232 ( |
.d_a(d_a), |
.q_a(q_a), |
.adr_a(adr_a), |
4361,7 → 4361,7
.clk_a(clk_a), |
.d_b({d_b,d_b}), |
.q_b(temp), |
.adr_b(adr_b), |
.adr_b(adr_b[b_addr_width-1:1]), |
.be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}), |
.we_b(we_b), |
.clk_b(clk_b) |
4380,7 → 4380,7
if (a_data_width==32 & b_data_width==64) begin : dpram_3264 |
logic [63:0] temp; |
`define MODULE dpram_be_2r2w |
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
`BASE`MODULE # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
`undef MODULE |
dpram6464 ( |
.d_a({d_a,d_a}), |
/versatile_library_actel.v
1719,8 → 1719,8
generate |
if (a_data_width==32 & b_data_width==16) begin : dpram_3216 |
logic [31:0] temp; |
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
dpram6464 ( |
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
dpram3232 ( |
.d_a(d_a), |
.q_a(q_a), |
.adr_a(adr_a), |
1729,7 → 1729,7
.clk_a(clk_a), |
.d_b({d_b,d_b}), |
.q_b(temp), |
.adr_b(adr_b), |
.adr_b(adr_b[b_addr_width-1:1]), |
.be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}), |
.we_b(we_b), |
.clk_b(clk_b) |
1744,7 → 1744,7
generate |
if (a_data_width==32 & b_data_width==64) begin : dpram_3264 |
logic [63:0] temp; |
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
dpram6464 ( |
.d_a({d_a,d_a}), |
.q_a(temp), |
/versatile_library_altera.v
1826,8 → 1826,8
generate |
if (a_data_width==32 & b_data_width==16) begin : dpram_3216 |
logic [31:0] temp; |
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
dpram6464 ( |
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
dpram3232 ( |
.d_a(d_a), |
.q_a(q_a), |
.adr_a(adr_a), |
1836,7 → 1836,7
.clk_a(clk_a), |
.d_b({d_b,d_b}), |
.q_b(temp), |
.adr_b(adr_b), |
.adr_b(adr_b[b_addr_width-1:1]), |
.be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}), |
.we_b(we_b), |
.clk_b(clk_b) |
1851,7 → 1851,7
generate |
if (a_data_width==32 & b_data_width==64) begin : dpram_3264 |
logic [63:0] temp; |
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
dpram6464 ( |
.d_a({d_a,d_a}), |
.q_a(temp), |
/memories.v
587,9 → 587,9
if (a_data_width==32 & b_data_width==16) begin : dpram_3216 |
logic [31:0] temp; |
`define MODULE dpram_be_2r2w |
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
`BASE`MODULE # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
`undef MODULE |
dpram6464 ( |
dpram3232 ( |
.d_a(d_a), |
.q_a(q_a), |
.adr_a(adr_a), |
598,7 → 598,7
.clk_a(clk_a), |
.d_b({d_b,d_b}), |
.q_b(temp), |
.adr_b(adr_b), |
.adr_b(adr_b[b_addr_width-1:1]), |
.be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}), |
.we_b(we_b), |
.clk_b(clk_b) |
617,7 → 617,7
if (a_data_width==32 & b_data_width==64) begin : dpram_3264 |
logic [63:0] temp; |
`define MODULE dpram_be_2r2w |
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
`BASE`MODULE # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
`undef MODULE |
dpram6464 ( |
.d_a({d_a,d_a}), |