URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl/verilog
- from Rev 42 to Rev 43
- ↔ Reverse comparison
Rev 42 → Rev 43
/versatile_library.v
25,6 → 25,7
`define MUX4_ANDOR |
`define MUX5_ANDOR |
`define MUX6_ANDOR |
`define PARITY |
|
`define ROM_INIT |
`define RAM |
1275,7 → 1276,49
|
endmodule |
`endif |
`ifdef CNT_BIN |
|
`ifdef PARITY |
|
`define MODULE parity_generate |
module `BASE`MODULE (data, parity); |
`undef MODULE |
parameter word_size = 32; |
parameter chunk_size = 8; |
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity |
input [word_size-1:0] data; |
output reg [word_size/chunk_size-1:0] parity; |
integer i,j; |
always @ (data) |
for (i=0;i<word_size/chunk_size;i=i+1) begin |
parity[i] = parity_type; |
for (j=0;j<chunk_size;j=j+1) begin |
parity[i] = data[i+j] ^ parity[i]; |
end |
end |
endmodule |
|
`define MODULE parity_check |
module `BASE`MODULE( data, parity, parity_error); |
`undef MODULE |
parameter word_size = 32; |
parameter chunk_size = 8; |
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity |
input [word_size-1:0] data; |
input [word_size/chunk_size-1:0] parity; |
output parity_error; |
reg [chunk_size-1:0] error_flag; |
integer i,j; |
always @ (data or parity) |
for (i=0;i<word_size/chunk_size;i=i+1) begin |
error_flag[i] = parity[i] ^ parity_type; |
for (j=0;j<chunk_size;j=j+1) begin |
error_flag[i] = data[i+j] ^ error_flag[i]; |
end |
end |
assign parity_error = |error_flag; |
endmodule |
|
`endif`ifdef CNT_BIN |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
/versatile_library_actel.v
502,6 → 502,39
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
endmodule |
module vl_parity_generate (data, parity); |
parameter word_size = 32; |
parameter chunk_size = 8; |
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity |
input [word_size-1:0] data; |
output reg [word_size/chunk_size-1:0] parity; |
integer i,j; |
always @ (data) |
for (i=0;i<word_size/chunk_size;i=i+1) begin |
parity[i] = parity_type; |
for (j=0;j<chunk_size;j=j+1) begin |
parity[i] = data[i+j] ^ parity[i]; |
end |
end |
endmodule |
module vl_parity_check( data, parity, parity_error); |
parameter word_size = 32; |
parameter chunk_size = 8; |
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity |
input [word_size-1:0] data; |
input [word_size/chunk_size-1:0] parity; |
output parity_error; |
reg [chunk_size-1:0] error_flag; |
integer i,j; |
always @ (data or parity) |
for (i=0;i<word_size/chunk_size;i=i+1) begin |
error_flag[i] = parity[i] ^ parity_type; |
for (j=0;j<chunk_size;j=j+1) begin |
error_flag[i] = data[i+j] ^ error_flag[i]; |
end |
end |
assign parity_error = |error_flag; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
/versatile_library_altera.v
610,6 → 610,39
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
endmodule |
module vl_parity_generate (data, parity); |
parameter word_size = 32; |
parameter chunk_size = 8; |
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity |
input [word_size-1:0] data; |
output reg [word_size/chunk_size-1:0] parity; |
integer i,j; |
always @ (data) |
for (i=0;i<word_size/chunk_size;i=i+1) begin |
parity[i] = parity_type; |
for (j=0;j<chunk_size;j=j+1) begin |
parity[i] = data[i+j] ^ parity[i]; |
end |
end |
endmodule |
module vl_parity_check( data, parity, parity_error); |
parameter word_size = 32; |
parameter chunk_size = 8; |
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity |
input [word_size-1:0] data; |
input [word_size/chunk_size-1:0] parity; |
output parity_error; |
reg [chunk_size-1:0] error_flag; |
integer i,j; |
always @ (data or parity) |
for (i=0;i<word_size/chunk_size;i=i+1) begin |
error_flag[i] = parity[i] ^ parity_type; |
for (j=0;j<chunk_size;j=j+1) begin |
error_flag[i] = data[i+j] ^ error_flag[i]; |
end |
end |
assign parity_error = |error_flag; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
/defines.v
25,6 → 25,7
`define MUX4_ANDOR |
`define MUX5_ANDOR |
`define MUX6_ANDOR |
`define PARITY |
|
`define ROM_INIT |
`define RAM |
/logic.v
162,3 → 162,46
|
endmodule |
`endif |
|
`ifdef PARITY |
|
`define MODULE parity_generate |
module `BASE`MODULE (data, parity); |
`undef MODULE |
parameter word_size = 32; |
parameter chunk_size = 8; |
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity |
input [word_size-1:0] data; |
output reg [word_size/chunk_size-1:0] parity; |
integer i,j; |
always @ (data) |
for (i=0;i<word_size/chunk_size;i=i+1) begin |
parity[i] = parity_type; |
for (j=0;j<chunk_size;j=j+1) begin |
parity[i] = data[i+j] ^ parity[i]; |
end |
end |
endmodule |
|
`define MODULE parity_check |
module `BASE`MODULE( data, parity, parity_error); |
`undef MODULE |
parameter word_size = 32; |
parameter chunk_size = 8; |
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity |
input [word_size-1:0] data; |
input [word_size/chunk_size-1:0] parity; |
output parity_error; |
reg [chunk_size-1:0] error_flag; |
integer i,j; |
always @ (data or parity) |
for (i=0;i<word_size/chunk_size;i=i+1) begin |
error_flag[i] = parity[i] ^ parity_type; |
for (j=0;j<chunk_size;j=j+1) begin |
error_flag[i] = data[i+j] ^ error_flag[i]; |
end |
end |
assign parity_error = |error_flag; |
endmodule |
|
`endif |