URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl/verilog
- from Rev 65 to Rev 66
- ↔ Reverse comparison
Rev 65 → Rev 66
/versatile_library.v
4703,7 → 4703,7
input [sw-1:0] wb_sel_i; |
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i; |
output [dw-1:0] wb_dat_o; |
output wb_ack_o; |
output [nr_of_ports-1:0] wb_ack_o; |
input wb_clk, wb_rst; |
|
wire [sw-1:0] cke; |
/versatile_library_actel.v
1986,7 → 1986,7
input [sw-1:0] wb_sel_i; |
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i; |
output [dw-1:0] wb_dat_o; |
output wb_ack_o; |
output [nr_of_ports-1:0] wb_ack_o; |
input wb_clk, wb_rst; |
wire [sw-1:0] cke; |
// local wb slave |
/wb.v
496,7 → 496,7
input [sw-1:0] wb_sel_i; |
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i; |
output [dw-1:0] wb_dat_o; |
output wb_ack_o; |
output [nr_of_ports-1:0] wb_ack_o; |
input wb_clk, wb_rst; |
|
wire [sw-1:0] cke; |
/versatile_library_altera.v
2091,7 → 2091,7
input [sw-1:0] wb_sel_i; |
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i; |
output [dw-1:0] wb_dat_o; |
output wb_ack_o; |
output [nr_of_ports-1:0] wb_ack_o; |
input wb_clk, wb_rst; |
wire [sw-1:0] cke; |
// local wb slave |