URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl
- from Rev 144 to Rev 145
- ↔ Reverse comparison
Rev 144 → Rev 145
/verilog/versatile_library.v
5012,7 → 5012,7
if (debug==1) begin : debug_we |
always @ (posedge clk) |
if (we3) |
$display ("Value %h written at register %h : time %t", d, adr, $time); |
$display ("Value %h written at register %h : time %t", wd3, a3, $time); |
end |
endgenerate |
|
/verilog/versatile_library_actel.v
3410,7 → 3410,7
if (debug==1) begin : debug_we |
always @ (posedge clk) |
if (we3) |
$display ("Value %h written at register %h : time %t", d, adr, $time); |
$display ("Value %h written at register %h : time %t", wd3, a3, $time); |
end |
endgenerate |
reg [data_width-1:0] wd3_reg; |
/verilog/versatile_library_altera.v
3505,7 → 3505,7
if (debug==1) begin : debug_we |
always @ (posedge clk) |
if (we3) |
$display ("Value %h written at register %h : time %t", d, adr, $time); |
$display ("Value %h written at register %h : time %t", wd3, a3, $time); |
end |
endgenerate |
vl_dpram_1r1w |
/verilog/memories.v
1102,7 → 1102,7
if (debug==1) begin : debug_we |
always @ (posedge clk) |
if (we3) |
$display ("Value %h written at register %h : time %t", d, adr, $time); |
$display ("Value %h written at register %h : time %t", wd3, a3, $time); |
end |
endgenerate |
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