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Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl
    from Rev 50 to Rev 51
    Reverse comparison

Rev 50 → Rev 51

/verilog/versatile_library.v
4653,6 → 4653,7
input [dat_width/8-1:0] wb_sel_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
output [dat_width-1:0] wb_dat_o;
reg [dat_width-1:0] wb_dat_o;
output stall_o;
output wb_ack_o;
reg wb_ack_o;
4660,7 → 4661,10
 
generate
if (dat_width==32) begin
reg [7:0] ram3, ram2, ram1, ram0 [1<<(adr_width-2)-1:0];
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
always @ (posedge wb_clk)
begin
if (wb_sel_i[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
4667,7 → 4671,7
if (wb_sel_i[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
if (wb_sel_i[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
if (wb_sel_i[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
wb_dat_o <= {ram3[adr_width-1:2],ram2[adr_width-1:2],ram1[adr_width-1:2],ram0[adr_width-1:2]};
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
end
end
endgenerate
/verilog/versatile_library_actel.v
1954,6 → 1954,7
input [dat_width/8-1:0] wb_sel_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
output [dat_width-1:0] wb_dat_o;
reg [dat_width-1:0] wb_dat_o;
output stall_o;
output wb_ack_o;
reg wb_ack_o;
1960,7 → 1961,10
input wb_clk, wb_rst;
generate
if (dat_width==32) begin
reg [7:0] ram3, ram2, ram1, ram0 [1<<(adr_width-2)-1:0];
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
always @ (posedge wb_clk)
begin
if (wb_sel_i[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
1967,7 → 1971,7
if (wb_sel_i[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
if (wb_sel_i[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
if (wb_sel_i[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
wb_dat_o <= {ram3[adr_width-1:2],ram2[adr_width-1:2],ram1[adr_width-1:2],ram0[adr_width-1:2]};
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
end
end
endgenerate
/verilog/wb.v
483,6 → 483,7
input [dat_width/8-1:0] wb_sel_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
output [dat_width-1:0] wb_dat_o;
reg [dat_width-1:0] wb_dat_o;
output stall_o;
output wb_ack_o;
reg wb_ack_o;
490,7 → 491,10
 
generate
if (dat_width==32) begin
reg [7:0] ram3, ram2, ram1, ram0 [1<<(adr_width-2)-1:0];
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
always @ (posedge wb_clk)
begin
if (wb_sel_i[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
497,7 → 501,7
if (wb_sel_i[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
if (wb_sel_i[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
if (wb_sel_i[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
wb_dat_o <= {ram3[adr_width-1:2],ram2[adr_width-1:2],ram1[adr_width-1:2],ram0[adr_width-1:2]};
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
end
end
endgenerate
/verilog/versatile_library_altera.v
2059,6 → 2059,7
input [dat_width/8-1:0] wb_sel_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
output [dat_width-1:0] wb_dat_o;
reg [dat_width-1:0] wb_dat_o;
output stall_o;
output wb_ack_o;
reg wb_ack_o;
2065,7 → 2066,10
input wb_clk, wb_rst;
generate
if (dat_width==32) begin
reg [7:0] ram3, ram2, ram1, ram0 [1<<(adr_width-2)-1:0];
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
always @ (posedge wb_clk)
begin
if (wb_sel_i[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
2072,7 → 2076,7
if (wb_sel_i[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
if (wb_sel_i[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
if (wb_sel_i[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
wb_dat_o <= {ram3[adr_width-1:2],ram2[adr_width-1:2],ram1[adr_width-1:2],ram0[adr_width-1:2]};
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
end
end
endgenerate

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