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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl
    from Rev 85 to Rev 86
    Reverse comparison

Rev 85 → Rev 86

/verilog/versatile_library.v
3751,10 → 3751,10
always_ff@(posedge clk)
begin
if(we) begin // note: we should have a for statement to support any bus width
if(be[3]) ram[adr[3] <= d[31:24];
if(be[2]) ram[adr[2] <= d[23:16];
if(be[1]) ram[adr[1] <= d[15:8];
if(be[0]) ram[adr[0] <= d[7:0];
if(be[3]) ram[adr][3] <= d[31:24];
if(be[2]) ram[adr][2] <= d[23:16];
if(be[1]) ram[adr][1] <= d[15:8];
if(be[0]) ram[adr][0] <= d[7:0];
end
q <= ram[adr];
end
5465,7 → 5465,7
.d(wbs_dat_i),
.adr(adr),
.be(wbs_sel_i),
.we(wbs_we_i & wb_ack_o),
.we(wbs_we_i & wbs_ack_o),
.q(wbs_dat_o),
.clk(wb_clk)
);
/verilog/versatile_library_actel.v
1266,10 → 1266,10
always_ff@(posedge clk)
begin
if(we) begin // note: we should have a for statement to support any bus width
if(be[3]) ram[adr[3] <= d[31:24];
if(be[2]) ram[adr[2] <= d[23:16];
if(be[1]) ram[adr[1] <= d[15:8];
if(be[0]) ram[adr[0] <= d[7:0];
if(be[3]) ram[adr][3] <= d[31:24];
if(be[2]) ram[adr][2] <= d[23:16];
if(be[1]) ram[adr][1] <= d[15:8];
if(be[0]) ram[adr][0] <= d[7:0];
end
q <= ram[adr];
end
2585,7 → 2585,7
.d(wbs_dat_i),
.adr(adr),
.be(wbs_sel_i),
.we(wbs_we_i & wb_ack_o),
.we(wbs_we_i & wbs_ack_o),
.q(wbs_dat_o),
.clk(wb_clk)
);
/verilog/wb.v
839,7 → 839,7
.d(wbs_dat_i),
.adr(adr),
.be(wbs_sel_i),
.we(wbs_we_i & wb_ack_o),
.we(wbs_we_i & wbs_ack_o),
.q(wbs_dat_o),
.clk(wb_clk)
);
/verilog/versatile_library_altera.v
1374,10 → 1374,10
always_ff@(posedge clk)
begin
if(we) begin // note: we should have a for statement to support any bus width
if(be[3]) ram[adr[3] <= d[31:24];
if(be[2]) ram[adr[2] <= d[23:16];
if(be[1]) ram[adr[1] <= d[15:8];
if(be[0]) ram[adr[0] <= d[7:0];
if(be[3]) ram[adr][3] <= d[31:24];
if(be[2]) ram[adr][2] <= d[23:16];
if(be[1]) ram[adr][1] <= d[15:8];
if(be[0]) ram[adr][0] <= d[7:0];
end
q <= ram[adr];
end
2690,7 → 2690,7
.d(wbs_dat_i),
.adr(adr),
.be(wbs_sel_i),
.we(wbs_we_i & wb_ack_o),
.we(wbs_we_i & wbs_ack_o),
.q(wbs_dat_o),
.clk(wb_clk)
);
/verilog/memories.v
140,10 → 140,10
always_ff@(posedge clk)
begin
if(we) begin // note: we should have a for statement to support any bus width
if(be[3]) ram[adr[3] <= d[31:24];
if(be[2]) ram[adr[2] <= d[23:16];
if(be[1]) ram[adr[1] <= d[15:8];
if(be[0]) ram[adr[0] <= d[7:0];
if(be[3]) ram[adr][3] <= d[31:24];
if(be[2]) ram[adr][2] <= d[23:16];
if(be[1]) ram[adr][1] <= d[15:8];
if(be[0]) ram[adr][0] <= d[7:0];
end
q <= ram[adr];
end

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