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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

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  • This comparison shows the changes necessary to convert path 
    /versatile_library/trunk
    from Rev 118 to Rev 119
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Rev 118 → Rev 119

/rtl/verilog/versatile_library.v
3979,7 → 3979,7
input we_a;
output reg [(data_width-1):0] q_b;
input clk_a, clk_b;
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
4032,7 → 4032,7
output reg [(data_width-1):0] q_a;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
4087,7 → 4087,7
input we_b;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
4148,7 → 4148,7
input we_b;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
/rtl/verilog/versatile_library_actel.v
1419,7 → 1419,7
input we_a;
output reg [(data_width-1):0] q_b;
input clk_a, clk_b;
reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
parameter debug = 0;
1459,7 → 1459,7
output reg [(data_width-1):0] q_a;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
parameter debug = 0;
1503,7 → 1503,7
input we_b;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
parameter debug = 0;
1554,7 → 1554,7
input we_b;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
parameter debug = 0;
/rtl/verilog/versatile_library_altera.v
1526,7 → 1526,7
input we_a;
output reg [(data_width-1):0] q_b;
input clk_a, clk_b;
reg [data_width-1:0] ram [mem_size-1:0] ;
reg [data_width-1:0] ram [0:mem_size-1] ;
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
parameter debug = 0;
1566,7 → 1566,7
output reg [(data_width-1):0] q_a;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_size-1:0] ;
reg [data_width-1:0] ram [0:mem_size-1] ;
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
parameter debug = 0;
1610,7 → 1610,7
input we_b;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_size-1:0] ;
reg [data_width-1:0] ram [0:mem_size-1] ;
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
parameter debug = 0;
1661,7 → 1661,7
input we_b;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_size-1:0] ;
reg [data_width-1:0] ram [0:mem_size-1] ;
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
parameter debug = 0;
/rtl/verilog/memories.v
216,7 → 216,7
input we_a;
output reg [(data_width-1):0] q_b;
input clk_a, clk_b;
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
269,7 → 269,7
output reg [(data_width-1):0] q_a;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
324,7 → 324,7
input we_b;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
385,7 → 385,7
input we_b;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";

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