URL
https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk
Subversion Repositories vhdl_wb_tb
Compare Revisions
- This comparison shows the changes necessary to convert path
/vhdl_wb_tb/trunk/rtl/vhdl/packages
- from Rev 4 to Rev 2
- ↔ Reverse comparison
Rev 4 → Rev 2
/convert_pkg.vhd
2,26 → 2,42
---- ---- |
---- VHDL Wishbone TESTBENCH ---- |
---- ---- |
---- This is a universal type conversion library for VHDL. With ---- |
---- the contained overloaded functions conversions from any to ---- |
---- any of the following data types are possible: ---- |
---- ---- |
---- std_logic_vector ---- |
---- std_ulogic_vector ---- |
---- unsigned ---- |
---- signed ---- |
---- bit_vector ---- |
---- integer ---- |
---- string ---- |
---- ---- |
---- To use them just add the prefix "to_" to the desired result ---- |
---- type with the source type in braces. ---- |
---- E.g. conversion from integer to std_logic_vector: ---- |
---- destination<=to_std_logic_vector(source); ---- |
---- ---- |
---- This file is part of the vhdl_wb_tb project ---- |
---- http://www.opencores.org/cores/vhdl_wb_tb/ ---- |
---- ---- |
---- This file contains some type conversion functions. ---- |
---- ---- |
---- To Do: ---- |
---- - ---- |
---- - ---- |
---- ---- |
---- Author(s): ---- |
---- - Sinx, sinx@opencores.org ---- |
---- - First & Last Name, email@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
-- SVN information |
-- |
-- $URL: $ |
-- $Revision: $ |
-- $Date: $ |
-- $Author: $ |
-- $Id: $ |
-- |
---------------------------------------------------------------------- |
---- SVN information |
---- |
---- $URL: $ |
---- $Revision: $ |
---- $Date: $ |
---- $Author: $ |
---- $Id: $ |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2018 Authors and OPENCORES.ORG ---- |
---- ---- |
47,12 → 63,15
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
-- library ----------------------------------------------------------- |
--============================================================================ |
--============================================================================ |
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
USE ieee.std_logic_arith.ALL; |
--============================================================================ |
|
-- package ----------------------------------------------------------- |
|
--============================================================================ |
PACKAGE convert_pkg IS |
|
FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector; |
62,20 → 81,22
FUNCTION to_string(slv : std_logic_vector; base : integer; length : integer) RETURN string; |
|
END convert_pkg; |
--============================================================================ |
|
-- package body ------------------------------------------------------ |
--============================================================================ |
PACKAGE BODY convert_pkg IS |
---------------------------------------------------------------------- |
--========================================================================== |
FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector IS |
BEGIN |
RETURN std_logic_vector(conv_unsigned(input, length)); |
END; |
---------------------------------------------------------------------- |
|
FUNCTION to_integer(input : std_logic_vector) RETURN integer IS |
BEGIN |
RETURN conv_integer(unsigned(input)); |
END; |
---------------------------------------------------------------------- |
|
--========================================================================== |
FUNCTION to_char(int : integer) RETURN character IS |
VARIABLE c : character; |
BEGIN |
120,7 → 141,10
END CASE; |
RETURN c; |
END to_char; |
---------------------------------------------------------------------- |
--======================================================================== |
-- convert integer to string using specified base |
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl) |
-- if base=0 convert to 32 bit hex |
FUNCTION to_string(int : integer; base : integer := 10; length : integer := 0) RETURN string IS |
|
VARIABLE temp : string(1 TO 1000); |
208,7 → 232,8
END IF; |
END IF; |
END to_string; |
---------------------------------------------------------------------- |
|
--======================================================================== |
FUNCTION to_string(slv : std_logic_vector) RETURN string IS |
|
VARIABLE hexlen : integer; |
251,13 → 276,14
END LOOP; |
RETURN hex(1 TO hexlen); |
END to_string; |
---------------------------------------------------------------------- |
|
--======================================================================== |
FUNCTION to_string(slv : std_logic_vector; base : integer; length : integer) RETURN string IS |
|
BEGIN |
RETURN to_string(to_integer(slv), base, length); |
END to_string; |
---------------------------------------------------------------------- |
|
end package body; |
---------------------------------------------------------------------- |
---- end of file ---- |
/my_project_pkg.vhd
1,27 → 1,31
---------------------------------------------------------------------- |
---- ---- |
---- VHDL Wishbone TESTBENCH ---- |
---- WISHBONE XXX IP Core ---- |
---- ---- |
---- This file is part of the vhdl_wb_tb project ---- |
---- http://www.opencores.org/cores/vhdl_wb_tb/ ---- |
---- This file is part of the XXX project ---- |
---- http://www.opencores.org/cores/xxx/ ---- |
---- ---- |
---- This file contains the project specific defines ---- |
---- Description ---- |
---- Implementation of XXX IP core according to ---- |
---- XXX IP core specification document. ---- |
---- ---- |
---- To Do: ---- |
---- - ---- |
---- - Adjust and rename this package for your project ---- |
---- - remove these comments ---- |
---- ---- |
---- Author(s): ---- |
---- - Sinx, sinx@opencores.org ---- |
---- - First & Last Name, email@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
-- SVN information |
-- |
-- $URL: $ |
-- $Revision: $ |
-- $Date: $ |
-- $Author: $ |
-- $Id: $ |
-- |
---------------------------------------------------------------------- |
---- SVN information |
---- |
---- $URL: $ |
---- $Revision: $ |
---- $Date: $ |
---- $Author: $ |
---- $Id: $ |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2018 Authors and OPENCORES.ORG ---- |
---- ---- |
47,22 → 51,20
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
-- library ----------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
library work; |
|
-- package ----------------------------------------------------------- |
package my_project_pkg is |
|
constant wishbone_address_width_c : integer := 32; |
constant wishbone_data_width_c : integer := 32; |
constant wishbone_data_of_unused_address_c : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADDEAD"; -- "X" might lead to less resources. Meaningful value might ease debugging |
constant wishbone_data_of_unused_address_p : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADBEEF"; -- "X" might lead to less resources. Meaningful value might ease debugging |
|
constant exit_simulator_at_tc_end_c : std_logic_vector := "0"; -- "1": exit simulator at end of tc_xxxx file. used for scripted simulation runs; |
-- "0": just pause simulator at end of tc_xxx file. used for manual simulation runs. |
|
subtype wishbone_tag_data_t is std_logic_vector(1 downto 0); |
subtype wishbone_tag_address_t is std_logic_vector(1 downto 0); |
subtype wishbone_tag_cycle_t is std_logic_vector(1 downto 0); |
72,9 → 74,6
constant zero_c : std_logic_vector(511 downto 0) := (others => '0'); |
end my_project_pkg; |
|
-- package body ------------------------------------------------------ |
package body my_project_pkg is |
end my_project_pkg; |
---------------------------------------------------------------------- |
---- end of file ---- |
---------------------------------------------------------------------- |
|
/wishbone_pkg.vhd
17,17 → 17,18
---- - ---- |
---- ---- |
---- Author(s): ---- |
---- - Sinx, sinx@opencores.org ---- |
---- - Sinx, email@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
-- SVN information |
-- |
-- $URL: $ |
-- $Revision: $ |
-- $Date: $ |
-- $Author: $ |
-- $Id: $ |
-- |
---------------------------------------------------------------------- |
---- SVN information |
---- |
---- $URL: $ |
---- $Revision: $ |
---- $Date: $ |
---- $Author: $ |
---- $Id: $ |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2018 Authors and OPENCORES.ORG ---- |
---- ---- |
53,10 → 54,12
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
|
-- library ----------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
library work; |
use work.my_project_pkg.all; |
|