URL
https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk
Subversion Repositories vhdl_wb_tb
Compare Revisions
- This comparison shows the changes necessary to convert path
/vhdl_wb_tb/trunk/bench/vhdl
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/stimulator.vhd
3,30 → 3,28
---- VHDL Wishbone TESTBENCH ---- |
---- ---- |
---- This file is part of the vhdl_wb_tb project ---- |
---- http://www.opencores.org/cores/vhdl_wb_tb/ ---- |
---- https://opencores.org/project/vhdl_wb_tb ---- |
---- ---- |
---- This file contains the top functional module of the design ---- |
---- under test. The top functional module will be enclosed by ---- |
---- the top module for synthesis or the tb_top for simulation. ---- |
---- The top module can contain some synthesis specific code, ---- |
---- where the tb_top contains simulation specific code. ---- |
---- This file contains the stimulator module of the design. ---- |
---- Modify the stimulator to stimulate your DUT ---- |
---- The stimulator is controlled by the testcase (tc_xxxx files)---- |
---- via a wishbone bus. ---- |
---- ---- |
---- To Do: ---- |
---- - ---- |
---- ---- |
---- Author(s): ---- |
---- - Sinx, email@opencores.org ---- |
---- - Sinx, sinx@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
-- SVN information |
-- |
-- $URL: $ |
-- $Revision: $ |
-- $Date: $ |
-- $Author: $ |
-- $Id: $ |
-- |
---------------------------------------------------------------------- |
---- SVN information |
---- |
---- $URL: $ |
---- $Revision: $ |
---- $Date: $ |
---- $Author: $ |
---- $Id: $ |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2018 Authors and OPENCORES.ORG ---- |
---- ---- |
124,6 → 122,6
signals_o <= s_register0(signals_o'left downto 0); |
--============================================================================ |
end rtl; --stimulator |
--============================================================================ |
-- end of file |
--============================================================================ |
---------------------------------------------------------------------- |
---- end of file ---- |
---------------------------------------------------------------------- |
/tb_pkg.vhd
5,31 → 5,24
---- This file is part of the vhdl_wb_tb project ---- |
---- http://www.opencores.org/cores/vhdl_wb_tb/ ---- |
---- ---- |
---- This file contains the highest (top) module of the test ---- |
---- bench. ---- |
---- It instantiates the design under test (DUT), instantiates ---- |
---- the stimulator module for test vector generation, ---- |
---- instantiates the verifier module for result comparison, ---- |
---- instantiates the test case top (testcase_top) bfm, ---- |
---- interconnects all three components, generates DUT-external ---- |
---- clocks and resets. ---- |
---- This file contains constants for the test bench, such as ---- |
---- register definitions. ---- |
---- ---- |
---- To Do: ---- |
---- - ---- |
---- ---- |
---- Author(s): ---- |
---- - Sinx, email@opencores.org ---- |
---- - Sinx, sinx@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
-- SVN information |
-- |
-- $URL: $ |
-- $Revision: $ |
-- $Date: $ |
-- $Author: $ |
-- $Id: $ |
-- |
---------------------------------------------------------------------- |
---- SVN information |
---- |
---- $URL: $ |
---- $Revision: $ |
---- $Date: $ |
---- $Author: $ |
---- $Id: $ |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2018 Authors and OPENCORES.ORG ---- |
---- ---- |
82,6 → 75,6
constant verifier_register2_c : integer := verifier_base_c + 16#0000_0008#; |
---------------------------------------------------------------------- |
end package; |
--============================================================================ |
-- end of file |
--============================================================================ |
---------------------------------------------------------------------- |
---- end of file ---- |
---------------------------------------------------------------------- |
/tb_top.vhd
3,10 → 3,14
---- VHDL Wishbone TESTBENCH ---- |
---- ---- |
---- This file is part of the vhdl_wb_tb project ---- |
---- http://www.opencores.org/cores/vhdl_wb_tb/ ---- |
---- https://opencores.org/project/vhdl_wb_tb ---- |
---- ---- |
---- This file contains the highest (top) module of the test ---- |
---- bench. ---- |
---- This file contains the highest (top) module for simulation. ---- |
---- Like tb_top it instantiates the core_top module and ---- |
---- provides parameters/generics. Where the top module provides ---- |
---- parameters for synthesis this file provides parameters for ---- |
---- simulation. ---- |
---- ---- |
---- It instantiates the design under test (DUT), instantiates ---- |
---- the stimulator module for test vector generation, ---- |
---- instantiates the verifier module for result comparison, ---- |
18,17 → 22,16
---- - ---- |
---- ---- |
---- Author(s): ---- |
---- - Sinx, email@opencores.org ---- |
---- - Sinx, sinx@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
-- SVN information |
-- |
-- $URL: $ |
-- $Revision: $ |
-- $Date: $ |
-- $Author: $ |
-- $Id: $ |
-- |
---- SVN information |
---- |
---- $URL: $ |
---- $Revision: $ |
---- $Date: $ |
---- $Author: $ |
---- $Id: $ |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2018 Authors and OPENCORES.ORG ---- |
71,13 → 74,10
-- in the tc_xxx files. |
end entity tb_top; |
|
--=architecture=============================================================== |
-- architecture ------------------------------------------------------ |
architecture rtl of tb_top is |
--============================================================================ |
----------------------------------------------------------------------------- |
constant g_wb_clock_period : time := 20.0 ns; -- 50 mhz |
--============================================================================ |
-- signal declaration |
--============================================================================ |
----------------------------------------------------------------------------- |
signal s_wb_bfm_out : wishbone_bfm_master_out_t; -- from testcase_top |
signal s_wb_bfm_in : wishbone_bfm_master_in_t; -- to testcase_top |
100,11 → 100,8
signal s_stimulus : std_logic_vector(number_of_stimulus_signals_c-1 downto 0); |
signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0); |
----------------------------------------------------------------------------- |
-- other signals |
|
begin |
----------------------------------------------------------------------------- |
begin |
--============================================================================ |
--clocks--------------------------------------------------------------------- |
wb_clock_generator : process -- required for test bench wb bus; 50mhz is standard |
begin |
128,7 → 125,7
s_wb_reset <= s_wb_reset_p2; |
----------------------------------------------------------------------------- |
-- instance of test case "player"; runs tc_xxxx modules |
testcase_top_inst : entity work.testcase_top |
tc_top_inst : entity work.tc_top |
port map ( |
wb_o => s_wb_bfm_out, |
wb_i => s_wb_bfm_in |
200,7 → 197,7
signals_i => s_verify |
); |
----------------------------------------------------------------------------- |
end rtl; |
--============================================================================ |
-- end of file |
--============================================================================ |
end rtl; |
---------------------------------------------------------------------- |
---- end of file ---- |
---------------------------------------------------------------------- |
/tc_top.vhd
0,0 → 1,76
---------------------------------------------------------------------- |
---- ---- |
---- VHDL Wishbone TESTBENCH ---- |
---- ---- |
---- This file is part of the vhdl_wb_tb project ---- |
---- http://www.opencores.org/cores/vhdl_wb_tb/ ---- |
---- ---- |
---- This file contains the top of the test case module. ---- |
---- It contains only an entity whereas the architecture is ---- |
---- located in several tc_xxxx files. ---- |
---- Every test case shall have its own tc_xxxx file. Every ---- |
---- tc_xxxx file needs to be compiled into the work library and ---- |
---- simulated independently. Use a script to run all tc_xxx ---- |
---- files automatically. ---- |
---- ---- |
---- To Do: ---- |
---- - ---- |
---- ---- |
---- Author(s): ---- |
---- - Sinx, sinx@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
---- SVN information |
---- |
---- $URL: $ |
---- $Revision: $ |
---- $Date: $ |
---- $Author: $ |
---- $Id: $ |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2018 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
|
-- library ----------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
library work; |
use work.convert_pkg.all; |
use work.my_project_pkg.all; |
use work.wishbone_pkg.all; |
use work.wishbone_bfm_pkg.all; |
|
-- entity ------------------------------------------------------------ |
entity tc_top is |
port ( |
wb_o : out wishbone_bfm_master_out_t; |
wb_i : in wishbone_bfm_master_in_t |
); |
end entity tc_top; |
---------------------------------------------------------------------- |
---- end of file ---- |
---------------------------------------------------------------------- |
/tc_xxxx.vhd
5,31 → 5,26
---- This file is part of the vhdl_wb_tb project ---- |
---- http://www.opencores.org/cores/vhdl_wb_tb/ ---- |
---- ---- |
---- This file contains the highest (top) module of the test ---- |
---- bench. ---- |
---- It instantiates the design under test (DUT), instantiates ---- |
---- the stimulator module for test vector generation, ---- |
---- instantiates the verifier module for result comparison, ---- |
---- instantiates the test case top (testcase_top) bfm, ---- |
---- interconnects all three components, generates DUT-external ---- |
---- clocks and resets. ---- |
---- This file contains the one test sequence for the test bench.---- |
---- Several test sequences shall be stored in several tc_xxxx ---- |
---- files. This file contains the architecture for the tc_top ---- |
---- enity, lcated in tc_top.vhd. ---- |
---- ---- |
---- To Do: ---- |
---- - ---- |
---- ---- |
---- Author(s): ---- |
---- - Sinx, email@opencores.org ---- |
---- - Sinx, sinx@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
-- SVN information |
-- |
-- $URL: $ |
-- $Revision: $ |
-- $Date: $ |
-- $Author: $ |
-- $Id: $ |
-- |
---------------------------------------------------------------------- |
---- SVN information |
---- |
---- $URL: $ |
---- $Revision: $ |
---- $Date: $ |
---- $Author: $ |
---- $Id: $ |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2018 Authors and OPENCORES.ORG ---- |
---- ---- |
68,16 → 63,15
use work.tb_pkg.all; |
|
-- architecture ------------------------------------------------------ |
architecture tc_xxxx of testcase_top is |
--========================================================================== |
architecture tc_xxxx of tc_top is |
---------------------------------------------------------------------- |
-- local constant definitions |
--========================================================================== |
--========================================================================== |
---------------------------------------------------------------------- |
begin |
--========================================================================== |
---------------------------------------------------------------------- |
tc_xxxx_proc : process |
begin |
--========================================================================== |
---------------------------------------------------------------------- |
-- standard signal initialization |
wb_o <= wb_bfm_master_out_idle_c; |
|
88,7 → 82,7
wait for 400 ns; |
wait until rising_edge(wb_i.clk); |
-- |
--========================================================================== |
---------------------------------------------------------------------- |
|
report "-----------------------------------------------------------------"; |
report "-- tc_xxxx: ADD_DESCRIPTION_HERE --"; |
140,22 → 134,23
wait until rising_edge(wb_i.clk); |
wb_read (verifier_register2_c, 16#0000_0005#, wb_i, wb_o); |
wait for 1 us; |
-- ================================================= |
---------------------------------------------------------------------- |
report "-- tc_xxxx finished"; |
-- ================================================= |
---------------------------------------------------------------------- |
-- |
wait for 400 ns; |
--wait; |
-- |
report "test case tc_xxxx completed successfully"; --severity failure; |
report "-----------------------------------------------------------------"; |
report "-----------------------------------------------------------------"; |
std.env.stop; -- pause simulation |
|
--std.env.finish; -- stop simulation; end modelsim |
wait for 100 ns; |
|
if (exit_simulator_at_tc_end_c/="1") then |
std.env.stop; -- pause simulation |
else |
std.env.finish; -- stop simulation |
end if; |
end process tc_xxxx_proc; |
--========================================================================== |
---------------------------------------------------------------------- |
end tc_xxxx; |
--============================================================================ |
-- end of file |
--============================================================================ |
---------------------------------------------------------------------- |
---- end of file ---- |
---------------------------------------------------------------------- |
/verifier.vhd
5,28 → 5,27
---- This file is part of the vhdl_wb_tb project ---- |
---- http://www.opencores.org/cores/vhdl_wb_tb/ ---- |
---- ---- |
---- This file contains the top functional module of the design ---- |
---- under test. The top functional module will be enclosed by ---- |
---- the top module for synthesis or the tb_top for simulation. ---- |
---- The top module can contain some synthesis specific code, ---- |
---- where the tb_top contains simulation specific code. ---- |
---- This file contains the verifier module which monitors the ---- |
---- DUTs responses. It is controlled via a wishbone interface ---- |
---- by the tc_xxxx files. ---- |
---- It can check the signals by itself or forward information ---- |
---- To the tc_xxxx files. ---- |
---- ---- |
---- To Do: ---- |
---- - ---- |
---- ---- |
---- Author(s): ---- |
---- - Sinx, email@opencores.org ---- |
---- - Sinx, sinx@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
-- SVN information |
-- |
-- $URL: $ |
-- $Revision: $ |
-- $Date: $ |
-- $Author: $ |
-- $Id: $ |
-- |
---------------------------------------------------------------------- |
---- SVN information |
---- |
---- $URL: $ |
---- $Revision: $ |
---- $Date: $ |
---- $Author: $ |
---- $Id: $ |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2018 Authors and OPENCORES.ORG ---- |
---- ---- |
76,14 → 75,14
); |
end verifier; |
|
--=architecture=============================================================== |
-- architecture ---------------------------------------------------------------- |
architecture rtl of verifier is |
--============================================================================ |
------------------------------------------------------------------------------ |
-- signal declaration |
--============================================================================ |
------------------------------------------------------------------------------ |
signal s_register0 : std_logic_vector(31 downto 0); |
signal s_register1 : std_logic_vector(31 downto 0); |
--============================================================================ |
------------------------------------------------------------------------------ |
begin |
------------------------------------------------------------------------------ |
wb_o.ack <= '1'; |
127,8 → 126,7
end process; |
|
------------------------------------------------------------------------------ |
--============================================================================ |
end rtl; --verifier |
--============================================================================ |
-- end of file |
--============================================================================ |
---------------------------------------------------------------------- |
---- end of file ---- |
---------------------------------------------------------------------- |
/wishbone_bfm_pkg.vhd
12,18 → 12,17
---- - ---- |
---- ---- |
---- Author(s): ---- |
---- - Sinx, email@opencores.org ---- |
---- - Sinx, sinx@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
-- SVN information |
-- |
-- $URL: $ |
-- $Revision: $ |
-- $Date: $ |
-- $Author: $ |
-- $Id: $ |
-- |
---------------------------------------------------------------------- |
---- SVN information |
---- |
---- $URL: $ |
---- $Revision: $ |
---- $Date: $ |
---- $Author: $ |
---- $Id: $ |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2018 Authors and OPENCORES.ORG ---- |
---- ---- |
108,36 → 107,36
tgc => (others=>'0'), |
we => '0' |
); |
---------------------------------------------------------------------- |
-- BUS FUNCTIONS ----------------------------------------------------- |
---------------------------------------------------------------------- |
---------------------------------------------------------------------- |
-- generate single write cycle |
PROCEDURE wb_write( |
address_i : IN integer; -- address to write to |
data_i : IN integer; -- data value to be written |
SIGNAL i : IN wishbone_bfm_master_in_t; -- incoming wb signals |
SIGNAL o : OUT wishbone_bfm_master_out_t; -- incoming wb signals |
display_error_message_i : IN integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all |
additional_error_message_i : IN string := "" |
procedure wb_write( |
address_i : in integer; -- address to write to |
data_i : in integer; -- data value to be written |
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals |
signal o : out wishbone_bfm_master_out_t; -- incoming wb signals |
display_error_message_i : in integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all |
additional_error_message_i : in string := "" |
); |
|
-- generate single read cycle and verify read word with expected_data_i |
PROCEDURE wb_read( |
address_i : IN INTEGER; |
expected_data_i : IN INTEGER; |
SIGNAL i : IN wishbone_bfm_master_in_t; |
SIGNAL o : OUT wishbone_bfm_master_out_t; |
display_error_message_i : IN integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp. |
additional_error_message_i : IN STRING := ""; |
expected_data_mask_i : IN INTEGER := 0 |
procedure wb_read( |
address_i : in integer; |
expected_data_i : in integer; |
signal i : in wishbone_bfm_master_in_t; |
signal o : out wishbone_bfm_master_out_t; |
display_error_message_i : in integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp. |
additional_error_message_i : in string := ""; |
expected_data_mask_i : in integer := 0 |
); |
|
-- generate single read cycle and return read data via read_data_o |
PROCEDURE wb_read( |
address_i : IN INTEGER; |
read_data_o : OUT STD_LOGIC_VECTOR (wishbone_address_width_c-1 DOWNTO 0); |
SIGNAL i : IN wishbone_bfm_master_in_t; |
SIGNAL o : OUT wishbone_bfm_master_out_t |
procedure wb_read( |
address_i : in integer; |
read_data_o : out std_logic_vector (wishbone_address_width_c-1 downto 0); |
signal i : in wishbone_bfm_master_in_t; |
signal o : out wishbone_bfm_master_out_t |
); |
---------------------------------------------------------------------- |
end; |
146,16 → 145,16
package body wishbone_bfm_pkg is |
---------------------------------------------------------------------- |
---------------------------------------------------------------------- |
PROCEDURE wb_write( |
address_i : IN integer; |
data_i : IN integer; |
SIGNAL i : IN wishbone_bfm_master_in_t; |
SIGNAL o : OUT wishbone_bfm_master_out_t; |
display_error_message_i : IN integer range 0 to 2 := 1; |
additional_error_message_i : IN string := "" |
) IS |
procedure wb_write( |
address_i : in integer; |
data_i : in integer; |
signal i : in wishbone_bfm_master_in_t; |
signal o : out wishbone_bfm_master_out_t; |
display_error_message_i : in integer range 0 to 2 := 1; |
additional_error_message_i : in string := "" |
) is |
---------------------------------------------------------------------- |
BEGIN |
begin |
o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c); |
o.dat <= to_std_logic_vector(data_i, wishbone_address_width_c); |
o.we <= '1'; |
167,29 → 166,29
o.stb <= '1'; |
o.tga <= (others => '0'); |
o.tgc <= (others => '0'); |
IF (display_error_message_i = 2) THEN |
REPORT "Writing :" & to_string(data_i, 16, wishbone_address_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4) & |
if (display_error_message_i = 2) then |
report "writing :" & to_string(data_i, 16, wishbone_address_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4) & |
additional_error_message_i; |
END IF; |
end if; |
|
WAIT UNTIL falling_edge(i.clk); |
wait until falling_edge(i.clk); |
-- wait for ack |
WHILE i.ack = '0' LOOP |
WAIT UNTIL falling_edge(i.clk); |
END LOOP; |
WAIT UNTIL rising_edge(i.clk); |
while i.ack = '0' loop |
wait until falling_edge(i.clk); |
end loop; |
wait until rising_edge(i.clk); |
o <= wb_bfm_master_out_idle_c; -- reset bus |
END wb_write; |
end wb_write; |
---------------------------------------------------------------------- |
---------------------------------------------------------------------- |
PROCEDURE wb_read( |
address_i : IN INTEGER; |
read_data_o : OUT STD_LOGIC_VECTOR (wishbone_address_width_c-1 DOWNTO 0); |
SIGNAL i : IN wishbone_bfm_master_in_t; |
SIGNAL o : OUT wishbone_bfm_master_out_t |
) IS |
procedure wb_read( |
address_i : in integer; |
read_data_o : out std_logic_vector (wishbone_address_width_c-1 downto 0); |
signal i : in wishbone_bfm_master_in_t; |
signal o : out wishbone_bfm_master_out_t |
) is |
---------------------------------------------------------------------- |
BEGIN |
begin |
o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c); |
o.dat <= (others => 'U'); |
o.we <= '0'; |
201,60 → 200,60
o.stb <= '1'; |
o.tga <= (others => '0'); |
o.tgc <= (others => '0'); |
WAIT UNTIL falling_edge(i.clk); |
wait until falling_edge(i.clk); |
-- ack handling |
WHILE (i.ack = '0') LOOP |
WAIT UNTIL falling_edge(i.clk); |
END LOOP; |
while (i.ack = '0') loop |
wait until falling_edge(i.clk); |
end loop; |
read_data_o := i.dat; |
WAIT UNTIL rising_edge(i.clk); |
wait until rising_edge(i.clk); |
o <= wb_bfm_master_out_idle_c; -- reset bus |
END wb_read; |
end wb_read; |
------------------------------------------------------------------------ |
------------------------------------------------------------------------ |
PROCEDURE wb_read( |
address_i : IN INTEGER; |
expected_data_i : IN INTEGER; |
SIGNAL i : IN wishbone_bfm_master_in_t; |
SIGNAL o : OUT wishbone_bfm_master_out_t; |
display_error_message_i : IN integer range 0 to 4 := 1; |
additional_error_message_i : IN STRING := ""; |
expected_data_mask_i : IN INTEGER := 0 |
) IS |
procedure wb_read( |
address_i : in integer; |
expected_data_i : in integer; |
signal i : in wishbone_bfm_master_in_t; |
signal o : out wishbone_bfm_master_out_t; |
display_error_message_i : in integer range 0 to 4 := 1; |
additional_error_message_i : in string := ""; |
expected_data_mask_i : in integer := 0 |
) is |
---------------------------------------------------------------------- |
VARIABLE readdata_v : STD_LOGIC_VECTOR (31 DOWNTO 0); |
VARIABLE diff_v : INTEGER; |
variable readdata_v : std_logic_vector (31 downto 0); |
variable diff_v : integer; |
---------------------------------------------------------------------- |
BEGIN |
begin |
wb_read(address_i,readdata_v,i,o); -- read from bus |
|
diff_v := to_integer(readdata_v) - expected_data_i; |
|
IF (display_error_message_i = 1) THEN -- output errors only |
IF (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) THEN |
REPORT "ERROR" & additional_error_message_i & ": Expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
if (display_error_message_i = 1) then -- output errors only |
if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) then |
report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4) |
SEVERITY error; |
END IF; |
ELSIF (display_error_message_i = 2) THEN -- Output all |
REPORT additional_error_message_i & ": Read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
severity error; |
end if; |
elsif (display_error_message_i = 2) then -- output all |
report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
" was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4) |
SEVERITY note; |
ELSIF (display_error_message_i = 3) THEN -- Output Filter |
IF ((readdata_v AND to_std_logic_vector(expected_data_mask_i, wishbone_address_width_c)) /= |
to_std_logic_vector(expected_data_i, wishbone_address_width_c)) THEN |
REPORT additional_error_message_i & ": Read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
severity note; |
elsif (display_error_message_i = 3) then -- output filter |
if ((readdata_v and to_std_logic_vector(expected_data_mask_i, wishbone_address_width_c)) /= |
to_std_logic_vector(expected_data_i, wishbone_address_width_c)) then |
report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
" was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4) |
SEVERITY note; |
END IF; |
ELSIF display_error_message_i = 4 THEN |
IF (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) THEN |
REPORT "ERROR" & additional_error_message_i & ": Expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4) & " Diff: " & to_string(readdata_v,16,wishbone_address_width_c/4) |
SEVERITY error; |
END IF; |
END IF; |
END wb_read; |
severity note; |
end if; |
elsif display_error_message_i = 4 then |
if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) then |
report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4) & " diff: " & to_string(readdata_v,16,wishbone_address_width_c/4) |
severity error; |
end if; |
end if; |
end wb_read; |
-------------------------------------------------------------------- |
end package body; |
---------------------------------------------------------------------- |