URL
https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk
Subversion Repositories vhdl_wb_tb
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- This comparison shows the changes necessary to convert path
/vhdl_wb_tb/trunk/rtl
- from Rev 2 to Rev 4
- ↔ Reverse comparison
Rev 2 → Rev 4
/vhdl/packages/convert_pkg.vhd
2,42 → 2,26
---- ---- |
---- VHDL Wishbone TESTBENCH ---- |
---- ---- |
---- This is a universal type conversion library for VHDL. With ---- |
---- the contained overloaded functions conversions from any to ---- |
---- any of the following data types are possible: ---- |
---- ---- |
---- std_logic_vector ---- |
---- std_ulogic_vector ---- |
---- unsigned ---- |
---- signed ---- |
---- bit_vector ---- |
---- integer ---- |
---- string ---- |
---- ---- |
---- To use them just add the prefix "to_" to the desired result ---- |
---- type with the source type in braces. ---- |
---- E.g. conversion from integer to std_logic_vector: ---- |
---- destination<=to_std_logic_vector(source); ---- |
---- ---- |
---- This file is part of the vhdl_wb_tb project ---- |
---- http://www.opencores.org/cores/vhdl_wb_tb/ ---- |
---- ---- |
---- This file contains some type conversion functions. ---- |
---- ---- |
---- To Do: ---- |
---- - ---- |
---- - ---- |
---- ---- |
---- Author(s): ---- |
---- - First & Last Name, email@opencores.org ---- |
---- - Sinx, sinx@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
-- SVN information |
-- |
-- $URL: $ |
-- $Revision: $ |
-- $Date: $ |
-- $Author: $ |
-- $Id: $ |
-- |
---------------------------------------------------------------------- |
---- SVN information |
---- |
---- $URL: $ |
---- $Revision: $ |
---- $Date: $ |
---- $Author: $ |
---- $Id: $ |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2018 Authors and OPENCORES.ORG ---- |
---- ---- |
63,15 → 47,12
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
--============================================================================ |
--============================================================================ |
-- library ----------------------------------------------------------- |
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
USE ieee.std_logic_arith.ALL; |
--============================================================================ |
|
|
--============================================================================ |
-- package ----------------------------------------------------------- |
PACKAGE convert_pkg IS |
|
FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector; |
81,22 → 62,20
FUNCTION to_string(slv : std_logic_vector; base : integer; length : integer) RETURN string; |
|
END convert_pkg; |
--============================================================================ |
|
--============================================================================ |
-- package body ------------------------------------------------------ |
PACKAGE BODY convert_pkg IS |
--========================================================================== |
---------------------------------------------------------------------- |
FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector IS |
BEGIN |
RETURN std_logic_vector(conv_unsigned(input, length)); |
END; |
|
---------------------------------------------------------------------- |
FUNCTION to_integer(input : std_logic_vector) RETURN integer IS |
BEGIN |
RETURN conv_integer(unsigned(input)); |
END; |
|
--========================================================================== |
---------------------------------------------------------------------- |
FUNCTION to_char(int : integer) RETURN character IS |
VARIABLE c : character; |
BEGIN |
141,10 → 120,7
END CASE; |
RETURN c; |
END to_char; |
--======================================================================== |
-- convert integer to string using specified base |
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl) |
-- if base=0 convert to 32 bit hex |
---------------------------------------------------------------------- |
FUNCTION to_string(int : integer; base : integer := 10; length : integer := 0) RETURN string IS |
|
VARIABLE temp : string(1 TO 1000); |
232,8 → 208,7
END IF; |
END IF; |
END to_string; |
|
--======================================================================== |
---------------------------------------------------------------------- |
FUNCTION to_string(slv : std_logic_vector) RETURN string IS |
|
VARIABLE hexlen : integer; |
276,14 → 251,13
END LOOP; |
RETURN hex(1 TO hexlen); |
END to_string; |
|
--======================================================================== |
---------------------------------------------------------------------- |
FUNCTION to_string(slv : std_logic_vector; base : integer; length : integer) RETURN string IS |
|
BEGIN |
RETURN to_string(to_integer(slv), base, length); |
END to_string; |
|
---------------------------------------------------------------------- |
end package body; |
---------------------------------------------------------------------- |
---- end of file ---- |
/vhdl/packages/my_project_pkg.vhd
1,31 → 1,27
---------------------------------------------------------------------- |
---- ---- |
---- WISHBONE XXX IP Core ---- |
---- VHDL Wishbone TESTBENCH ---- |
---- ---- |
---- This file is part of the XXX project ---- |
---- http://www.opencores.org/cores/xxx/ ---- |
---- This file is part of the vhdl_wb_tb project ---- |
---- http://www.opencores.org/cores/vhdl_wb_tb/ ---- |
---- ---- |
---- Description ---- |
---- Implementation of XXX IP core according to ---- |
---- XXX IP core specification document. ---- |
---- This file contains the project specific defines ---- |
---- ---- |
---- To Do: ---- |
---- - Adjust and rename this package for your project ---- |
---- - remove these comments ---- |
---- - ---- |
---- ---- |
---- Author(s): ---- |
---- - First & Last Name, email@opencores.org ---- |
---- - Sinx, sinx@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
-- SVN information |
-- |
-- $URL: $ |
-- $Revision: $ |
-- $Date: $ |
-- $Author: $ |
-- $Id: $ |
-- |
---------------------------------------------------------------------- |
---- SVN information |
---- |
---- $URL: $ |
---- $Revision: $ |
---- $Date: $ |
---- $Author: $ |
---- $Id: $ |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2018 Authors and OPENCORES.ORG ---- |
---- ---- |
51,20 → 47,22
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
|
-- library ----------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
library work; |
|
-- package ----------------------------------------------------------- |
package my_project_pkg is |
|
constant wishbone_address_width_c : integer := 32; |
constant wishbone_data_width_c : integer := 32; |
constant wishbone_data_of_unused_address_c : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADDEAD"; -- "X" might lead to less resources. Meaningful value might ease debugging |
constant wishbone_data_of_unused_address_p : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADBEEF"; -- "X" might lead to less resources. Meaningful value might ease debugging |
|
constant exit_simulator_at_tc_end_c : std_logic_vector := "0"; -- "1": exit simulator at end of tc_xxxx file. used for scripted simulation runs; |
-- "0": just pause simulator at end of tc_xxx file. used for manual simulation runs. |
|
subtype wishbone_tag_data_t is std_logic_vector(1 downto 0); |
subtype wishbone_tag_address_t is std_logic_vector(1 downto 0); |
subtype wishbone_tag_cycle_t is std_logic_vector(1 downto 0); |
74,6 → 72,9
constant zero_c : std_logic_vector(511 downto 0) := (others => '0'); |
end my_project_pkg; |
|
-- package body ------------------------------------------------------ |
package body my_project_pkg is |
end my_project_pkg; |
|
---------------------------------------------------------------------- |
---- end of file ---- |
---------------------------------------------------------------------- |
/vhdl/packages/wishbone_pkg.vhd
17,18 → 17,17
---- - ---- |
---- ---- |
---- Author(s): ---- |
---- - Sinx, email@opencores.org ---- |
---- - Sinx, sinx@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
-- SVN information |
-- |
-- $URL: $ |
-- $Revision: $ |
-- $Date: $ |
-- $Author: $ |
-- $Id: $ |
-- |
---------------------------------------------------------------------- |
---- SVN information |
---- |
---- $URL: $ |
---- $Revision: $ |
---- $Date: $ |
---- $Author: $ |
---- $Id: $ |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2018 Authors and OPENCORES.ORG ---- |
---- ---- |
54,12 → 53,10
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
|
-- library ----------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
library work; |
use work.my_project_pkg.all; |
|
/vhdl/core_top.vhd
15,18 → 15,17
---- - ---- |
---- ---- |
---- Author(s): ---- |
---- - Sinx, email@opencores.org ---- |
---- - Sinx, sinx@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
-- SVN information |
-- |
-- $URL: $ |
-- $Revision: $ |
-- $Date: $ |
-- $Author: $ |
-- $Id: $ |
-- |
---------------------------------------------------------------------- |
---- SVN information |
---- |
---- $URL: $ |
---- $Revision: $ |
---- $Date: $ |
---- $Author: $ |
---- $Id: $ |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2018 Authors and OPENCORES.ORG ---- |
---- ---- |
75,14 → 74,14
); |
end core_top; |
|
--=architecture=============================================================== |
-- architecture ------------------------------------------------------ |
architecture rtl of core_top is |
--============================================================================ |
------------------------------------------------------------------------------ |
-- signal declaration |
--============================================================================ |
------------------------------------------------------------------------------ |
signal shift_register_r : std_logic_vector (g_number_of_out_signals-1 downto 0); |
signal old_shift_clock_r : std_logic := '0'; |
--============================================================================ |
------------------------------------------------------------------------------ |
begin |
------------------------------------------------------------------------------ |
-- module instantiation |
101,11 → 100,7
------------------------------------------------------------------------------ |
signals_o <= shift_register_r; |
------------------------------------------------------------------------------ |
------------------------------------------------------------------------------ |
------------------------------------------------------------------------------ |
------------------------------------------------------------------------------ |
--============================================================================ |
end rtl; --core_top |
--============================================================================ |
-- end of file |
--============================================================================ |
end rtl; |
---------------------------------------------------------------------- |
---- end of file ---- |
---------------------------------------------------------------------- |
/vhdl/top.vhd
3,33 → 3,29
---- VHDL Wishbone TESTBENCH ---- |
---- ---- |
---- This file is part of the vhdl_wb_tb project ---- |
---- http://www.opencores.org/cores/vhdl_wb_tb/ ---- |
---- https://opencores.org/project/vhdl_wb_tb ---- |
---- ---- |
---- This file contains the highest (top) module of the test ---- |
---- bench. ---- |
---- It instantiates the design under test (DUT), instantiates ---- |
---- the stimulator module for test vector generation, ---- |
---- instantiates the verifier module for result comparison, ---- |
---- instantiates the test case top (testcase_top) bfm, ---- |
---- interconnects all three components, generates DUT-external ---- |
---- clocks and resets. ---- |
---- This file contains the highest (top) module for synthesis. ---- |
---- Like tb_top it instantiates the core_top module and ---- |
---- provides parameters/generics. Where the tb_top module ---- |
---- provides parameters for simulation this file provides ---- |
---- parameters for synthesis. ---- |
---- ---- |
---- To Do: ---- |
---- - ---- |
---- ---- |
---- Author(s): ---- |
---- - Sinx, email@opencores.org ---- |
---- - Sinx, sinx@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
-- SVN information |
-- |
-- $URL: $ |
-- $Revision: $ |
-- $Date: $ |
-- $Author: $ |
-- $Id: $ |
-- |
---------------------------------------------------------------------- |
---- SVN information |
---- |
---- $URL: $ |
---- $Revision: $ |
---- $Date: $ |
---- $Author: $ |
---- $Id: $ |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2018 Authors and OPENCORES.ORG ---- |
---- ---- |
73,16 → 69,14
); |
end entity top; |
|
--=architecture=============================================================== |
-- architecture ------------------------------------------------------ |
architecture rtl of top is |
--============================================================================ |
-- signal declaration |
--============================================================================ |
----------------------------------------------------------------------------- |
-- constant number_of_stimulus_signals_c : integer := 8; |
-- signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0); |
----------------------------------------------------------------------------- |
begin |
--============================================================================ |
----------------------------------------------------------------------------- |
-- instance of design |
core_top_inst : entity work.core_top |
generic map( |
97,6 → 91,6
); |
----------------------------------------------------------------------------- |
end rtl; |
--============================================================================ |
-- end of file |
--============================================================================ |
---------------------------------------------------------------------- |
---- end of file ---- |
---------------------------------------------------------------------- |