URL
https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk
Subversion Repositories vhdl_wb_tb
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- This comparison shows the changes necessary to convert path
/vhdl_wb_tb/trunk/rtl_sim/run
- from Rev 16 to Rev 24
- ↔ Reverse comparison
Rev 16 → Rev 24
/sim.mpf
169,7 → 169,7
; %I - Instance or Region pathname (if available) |
; %% - print '%' character |
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" |
AssertionFormat = "** [%I] %T %S %R\n" |
AssertionFormat = "** %T %S %R\n" |
|
; Assertion File - alternate file for storing VHDL/Verilog assertion messages |
; AssertFile = assert.log |