URL
https://opencores.org/ocsvn/wb_vga/wb_vga/trunk
Subversion Repositories wb_vga
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- from Rev 3 to Rev 4
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Rev 3 → Rev 4
/trunk/TestBench/vga_chip_TB.vhd
File deleted
/trunk/TestBench/palette_TB.vhd
0,0 → 1,163
library ieee,wb_tk,wb_vga; |
use ieee.NUMERIC_STD.all; |
use ieee.std_logic_1164.all; |
use wb_tk.technology.all; |
use wb_tk.wb_test.all; |
use wb_tk.all; |
use wb_vga.all; |
|
entity wb_pal_ram_tb is |
generic( |
cpu_dat_width: positive := 32; |
cpu_adr_width: positive := 8; |
v_dat_width: positive := 16; |
v_adr_width: positive := 8 |
); |
end wb_pal_ram_tb; |
|
architecture TB of wb_pal_ram_tb is |
component wb_pal_ram |
generic ( |
cpu_dat_width: positive := cpu_dat_width; |
cpu_adr_width: positive := cpu_adr_width; |
v_dat_width: positive := v_dat_width; |
v_adr_width: positive := v_adr_width |
); |
port ( |
-- Wishbone interface to CPU (write-only support) |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
adr_i: in std_logic_vector (cpu_adr_width-1 downto 0); |
-- sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
cyc_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
err_o: out std_logic; |
err_oi: in std_logic := '-'; |
-- rty_o: out std_logic; |
-- rty_oi: in std_logic := '-'; |
we_i: in std_logic; |
stb_i: in std_logic; |
-- Interface to the video output |
blank: in std_logic; |
v_dat_i: in std_logic_vector(v_adr_width-1 downto 0); |
v_dat_o: out std_logic_vector(v_dat_width-1 downto 0) |
); |
end component; |
|
-- Wishbone interface to CPU (write-only support) |
signal clk_i: std_logic; |
signal rst_i: std_logic := '0'; |
signal adr_i: std_logic_vector (cpu_adr_width-1 downto 0); |
signal dat_i: std_logic_vector (cpu_dat_width-1 downto 0); |
signal dat_oi: std_logic_vector (cpu_dat_width-1 downto 0) := (others => '-'); |
signal dat_o: std_logic_vector (cpu_dat_width-1 downto 0); |
signal cyc_i: std_logic; |
signal ack_o: std_logic; |
signal ack_oi: std_logic := '-'; |
signal err_o: std_logic; |
signal err_oi: std_logic := '-'; |
signal we_i: std_logic; |
signal stb_i: std_logic; |
-- Interface to the video output |
signal blank: std_logic; |
signal v_dat_i: std_logic_vector(v_adr_width-1 downto 0); |
signal v_dat_o: std_logic_vector(v_dat_width-1 downto 0); |
begin |
|
-- Unit Under Test port map |
UUT : wb_pal_ram |
port map ( |
clk_i => clk_i, |
rst_i => rst_i, |
adr_i => adr_i, |
dat_i => dat_i, |
dat_oi => dat_oi, |
dat_o => dat_o, |
cyc_i => cyc_i, |
ack_o => ack_o, |
ack_oi => ack_oi, |
err_o => err_o, |
err_oi => err_oi, |
we_i => we_i, |
stb_i => stb_i, |
|
blank => blank, |
v_dat_i => v_dat_i, |
v_dat_o => v_dat_o |
); |
|
clk: process is |
begin |
clk_i <= '0'; |
wait for 25ns; |
clk_i <= '1'; |
wait for 25ns; |
end process; |
|
reset: process is |
begin |
rst_i <= '1'; |
wait for 150ns; |
rst_i <= '0'; |
wait; |
end process; |
|
gen_v_output: process is |
variable addr: std_logic_vector(v_adr_width-1 downto 0) := (others => '0'); |
begin |
blank <= '0'; |
wait until clk_i'EVENT and clk_i = '1'; |
v_dat_i <= addr; |
-- if (addr = "1111") then |
-- blank <= '1'; |
-- wait until clk_i'EVENT and clk_i = '1'; |
-- addr := (v_adr_width'RANGE => '0'); |
-- else |
addr := add_one(addr); |
-- end if; |
end process; |
|
dat_oi <= (others => 'U'); |
ack_oi <= 'U'; |
err_oi <= 'U'; |
|
master: process is |
variable i: integer := 0; |
variable addr: std_logic_vector(cpu_adr_width-1 downto 0) := (others => '0'); |
variable data: std_logic_vector(cpu_dat_width-1 downto 0) := (others => '0'); |
begin |
we_i <= '0'; |
cyc_i <= '0'; |
stb_i <= '0'; |
adr_i <= (others => '0'); |
dat_i <= (others => '0'); |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
|
for i in 0 to 511 loop |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,addr,data); |
addr := add_one(addr); |
data := add_one(data); |
end loop; |
wait; |
end process; |
|
end TB; |
|
configuration TB_wb_pal_ram of wb_pal_ram_tb is |
for TB |
for UUT : wb_pal_ram |
use entity wb_vga.wb_pal_ram(wb_pal_ram); |
end for; |
end for; |
end TB_wb_pal_ram; |
|
/trunk/TestBench/accel_TB.vhd
0,0 → 1,226
library ieee,wb_tk,wb_vga; |
use ieee.NUMERIC_STD.all; |
use ieee.std_logic_1164.all; |
use wb_tk.technology.all; |
use wb_tk.wb_test.all; |
use wb_tk.all; |
use wb_vga.all; |
|
entity accel_tb is |
generic( |
accel_size : POSITIVE := 9; |
video_addr_width : POSITIVE := 20; |
video_data_width : POSITIVE := 16; |
data_width : POSITIVE := 16 ); |
end accel_tb; |
|
architecture TB of accel_tb is |
component accel |
generic( |
accel_size : POSITIVE := accel_size; |
video_addr_width : POSITIVE := video_addr_width; |
video_data_width : POSITIVE := video_data_width; |
data_width : POSITIVE := data_width |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- Slave interface to the CPU side |
we_i: in std_logic; |
cyc_i: in std_logic; |
sel_i: in std_logic_vector ((data_width/8)-1 downto 0) := (others => '1'); |
cur_stb_i: in std_logic; |
ext_stb_i: in std_logic; |
acc_stb_i: in std_logic; |
mem_stb_i: in std_logic; |
|
adr_i: in std_logic_vector(accel_size-1 downto 0); |
dat_i: in std_logic_vector(data_width-1 downto 0); |
dat_o: out std_logic_vector(data_width-1 downto 0); |
dat_oi: in std_logic_vector(data_width-1 downto 0); |
|
ack_o: out std_logic; |
ack_oi: in std_logic; |
|
-- Master interface to the video memory side. |
v_we_o: out std_logic; |
v_cyc_o: out std_logic; |
v_sel_o: out std_logic; |
|
v_adr_o: out std_logic_vector (video_addr_width-1 downto 0); |
v_dat_o: out std_logic_vector (video_data_width-1 downto 0); |
v_dat_i: in std_logic_vector (video_data_width-1 downto 0); |
|
v_ack_i: in std_logic |
); |
end component; |
|
-- Stimulus signals - signals mapped to the input and inout ports of tested entity |
signal clk_i : std_logic; |
signal rst_i : std_logic; |
signal we_i : std_logic; |
signal cyc_i : std_logic; |
signal sel_i: std_logic_vector ((data_width/8)-1 downto 0) := (others => '1'); |
signal cur_stb_i : std_logic; |
signal ext_stb_i : std_logic; |
signal acc_stb_i : std_logic; |
signal mem_stb_i : std_logic; |
signal adr_i : std_logic_vector((accel_size-1) downto 0); |
signal dat_i : std_logic_vector((data_width-1) downto 0); |
signal dat_oi : std_logic_vector((data_width-1) downto 0); |
signal ack_oi : std_logic; |
signal v_dat_i : std_logic_vector((video_data_width-1) downto 0); |
signal v_ack_i : std_logic; |
-- Observed signals - signals mapped to the output ports of tested entity |
signal dat_o : std_logic_vector((data_width-1) downto 0); |
signal ack_o : std_logic; |
signal v_we_o : std_logic; |
signal v_sel_o : std_logic; |
signal v_cyc_o : std_logic; |
signal v_adr_o : std_logic_vector((video_addr_width-1) downto 0); |
signal v_dat_o : std_logic_vector((video_data_width-1) downto 0); |
begin |
|
-- Unit Under Test port map |
UUT : accel |
port map |
(clk_i => clk_i, |
rst_i => rst_i, |
we_i => we_i, |
cyc_i => cyc_i, |
sel_i => sel_i, |
cur_stb_i => cur_stb_i, |
ext_stb_i => ext_stb_i, |
acc_stb_i => acc_stb_i, |
mem_stb_i => mem_stb_i, |
adr_i => adr_i, |
dat_i => dat_i, |
dat_o => dat_o, |
dat_oi => dat_oi, |
ack_o => ack_o, |
ack_oi => ack_oi, |
v_we_o => v_we_o, |
v_cyc_o => v_cyc_o, |
v_sel_o => v_sel_o, |
v_adr_o => v_adr_o, |
v_dat_o => v_dat_o, |
v_dat_i => v_dat_i, |
v_ack_i => v_ack_i ); |
|
clk: process is |
begin |
clk_i <= '0'; |
wait for 25ns; |
clk_i <= '1'; |
wait for 25ns; |
end process; |
|
reset: process is |
begin |
rst_i <= '1'; |
wait for 150ns; |
rst_i <= '0'; |
wait; |
end process; |
|
memory: process is |
begin |
v_ack_i <= '0'; |
v_dat_i <= (others => 'U'); |
if (v_sel_o /= '1') then wait until v_sel_o = '1'; end if; |
wait until clk_i'EVENT and clk_i = '1'; |
v_ack_i <= '1'; |
if (v_we_o = '1') then |
v_dat_i <= v_adr_o(v_dat_i'RANGE); |
else |
v_dat_i <= (others => 'U'); |
end if; |
wait until clk_i'EVENT and clk_i = '1'; |
wait for 15ns; |
end process; |
|
dat_oi <= (others => 'U'); |
ack_oi <= 'U'; |
|
master: process is |
variable init: boolean := true; |
begin |
if (init) then |
we_i <= '0'; |
cyc_i <= '0'; |
cur_stb_i <= '0'; |
ext_stb_i <= '0'; |
acc_stb_i <= '0'; |
mem_stb_i <= '0'; |
adr_i <= (others => '0'); |
dat_i <= (others => '0'); |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
|
-- Set Cursor to 0 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000000000"); |
-- Accel index 0 is 0 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000000","0000000000000000"); |
-- Accel index 1 is 1 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000001","0000000000000001"); |
-- Accel index 2 is 3 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000010","0000000000000011"); |
-- Accel index 3 is -1 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000011","1111111111111111"); |
end if; |
init := false; |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000000","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000"); |
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000000001"); |
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000"); |
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000001000"); |
|
-- Set Cursor to 16 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000010000"); |
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000000","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000"); |
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000010001"); |
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000"); |
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000011000"); |
|
-- Set Cursor to 0 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000000000"); |
|
wait; |
end process; |
|
end TB; |
|
configuration TB_accel of accel_tb is |
for TB |
for UUT : accel |
use entity wb_vga.accel(accel); |
end for; |
end for; |
end TB_accel; |
|
/trunk/mem_reader.vhd
8,8 → 8,8
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library work; |
use work.technology.all; |
library wb_tk; |
use wb_tk.technology.all; |
|
entity mem_reader is |
generic ( |
190,7 → 190,7
end if; |
v_mem_addr <= pixel_cnt; |
end process; |
v_mem_rd <= not video_fifo_full; |
v_mem_rd <= (not video_fifo_full) and (not reset); |
|
-- Pixel data output state machine. |
pixel_output: process is |
/trunk/vga_chip.vhd
8,6 → 8,27
library IEEE; |
use IEEE.std_logic_1164.all; |
|
package constants is |
constant v_dat_width: positive := 16; |
constant v_adr_width : positive := 20; |
constant cpu_dat_width: positive := 8; |
constant cpu_adr_width: positive := 21; |
constant fifo_size: positive := 256; |
-- constant addr_diff: integer := log2(cpu_dat_width/v_dat_width); |
end constants; |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library wb_vga; |
use wb_vga.all; |
use wb_vga.constants.all; |
|
library wb_tk; |
use wb_tk.all; |
use wb_tk.technology.all; |
|
|
-- same as VGA_CORE but without generics. Suited for post-layout simulation. |
entity vga_chip is |
port ( |
16,9 → 37,9
rst_i: in std_logic := '0'; |
|
-- CPU bus interface |
dat_i: in std_logic_vector (8-1 downto 0); |
dat_oi: in std_logic_vector (8-1 downto 0); |
dat_o: out std_logic_vector (8-1 downto 0); |
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
cyc_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic; |
25,11 → 46,12
we_i: in std_logic; |
vmem_stb_i: in std_logic; |
reg_stb_i: in std_logic; |
adr_i: in std_logic_vector (20 downto 0); |
adr_i: in std_logic_vector (cpu_adr_width-1 downto 0); |
sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
|
-- video memory SRAM interface |
s_data : inout std_logic_vector((16-1) downto 0); |
s_addr : out std_logic_vector((20-1) downto 0); |
s_data : inout std_logic_vector(v_dat_width-1 downto 0); |
s_addr : out std_logic_vector(v_adr_width-1 downto 0); |
s_oen : out std_logic; |
s_wrhn : out std_logic; |
s_wrln : out std_logic; |
43,53 → 65,84
h_tc: out std_logic; |
v_tc: out std_logic; |
blank: out std_logic; |
video_out: out std_logic_vector (7 downto 0); -- video output binary signal (unused bits are forced to 0) |
|
-- TEST SIGNALS |
T_v_we_o: out std_logic; |
T_v_stb_o: out std_logic; |
T_v_ack_i: out std_logic; |
T_v_adr_o : out std_logic_vector((20-1) downto 0); |
T_v_sel_o : out std_logic_vector((16/8)-1 downto 0); |
T_v_dat_o : out std_logic_vector((16-1) downto 0); |
T_v_dat_i : out std_logic_vector((16-1) downto 0) |
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0) |
); |
end vga_chip; |
|
architecture vga_chip of vga_chip is |
component wb_async_slave |
generic ( |
width: positive := 16; |
addr_width: positive := 20 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- interface for wait-state generator state-machine |
wait_state: in std_logic_vector (3 downto 0); |
|
-- interface to wishbone master device |
adr_i: in std_logic_vector (addr_width-1 downto 0); |
sel_i: in std_logic_vector ((addr_width/8)-1 downto 0); |
dat_i: in std_logic_vector (width-1 downto 0); |
dat_o: out std_logic_vector (width-1 downto 0); |
dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-'); |
we_i: in std_logic; |
stb_i: in std_logic; |
ack_o: out std_logic := '0'; |
ack_oi: in std_logic := '-'; |
|
-- interface to async slave |
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z'); |
a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U'); |
a_rdn: out std_logic := '1'; |
a_wrn: out std_logic := '1'; |
a_cen: out std_logic := '1'; |
-- byte-enable signals |
a_byen: out std_logic_vector ((width/8)-1 downto 0) |
); |
end component; |
|
component vga_core |
generic ( |
-- cannot be overwritten at the moment... |
v_mem_width: positive := 16; |
fifo_size: positive := 256; |
v_addr_width : positive := 20; |
bus_width: positive := 8 |
v_dat_width: positive := 16; |
v_adr_width : positive := 20; |
cpu_dat_width: positive := 8; |
cpu_adr_width: positive := 21; |
fifo_size: positive := 256 |
); |
port ( |
clk_i: in std_logic; |
clk_en: in std_logic := '1'; |
rst_i: in std_logic := '0'; |
|
|
-- CPU bus interface |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
cyc_i: in std_logic; |
we_i: in std_logic; |
vmem_stb_i: in std_logic; -- selects video memory |
total_stb_i: in std_logic; -- selects total register |
ofs_stb_i: in std_logic; -- selects offset register |
reg_bank_stb_i: in std_logic; -- selects all other registers (in a single bank) |
ack_o: out std_logic; |
ack_oi: in std_logic; |
we_i: in std_logic; |
vmem_stb_i: in std_logic; |
reg_stb_i: in std_logic; |
adr_i: in std_logic_vector (v_addr_width downto 0); |
|
-- video memory SRAM interface |
s_data : inout std_logic_vector((v_mem_width-1) downto 0); |
s_addr : out std_logic_vector((v_addr_width-1) downto 0); |
s_oen : out std_logic; |
s_wrhn : out std_logic; |
s_wrln : out std_logic; |
s_cen : out std_logic; |
|
adr_i: in std_logic_vector (v_adr_width downto 0); |
sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
|
-- video memory interface |
v_adr_o: out std_logic_vector (v_adr_width-1 downto 0); |
v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0); |
v_dat_i: in std_logic_vector (v_dat_width-1 downto 0); |
v_dat_o: out std_logic_vector (v_dat_width-1 downto 0); |
v_cyc_o: out std_logic; |
v_ack_i: in std_logic; |
v_we_o: out std_logic; |
v_stb_o: out std_logic; |
|
-- sync blank and video signal outputs |
h_sync: out std_logic; |
h_blank: out std_logic; |
98,40 → 151,106
h_tc: out std_logic; |
v_tc: out std_logic; |
blank: out std_logic; |
video_out: out std_logic_vector (7 downto 0); -- video output binary signal (unused bits are forced to 0) |
|
-- TEST SIGNALS |
T_v_we_o: out std_logic; |
T_v_stb_o: out std_logic; |
T_v_ack_i: out std_logic; |
T_v_adr_o : out std_logic_vector((v_addr_width-1) downto 0); |
T_v_sel_o : out std_logic_vector((v_addr_width/8)-1 downto 0); |
T_v_dat_o : out std_logic_vector((v_mem_width-1) downto 0); |
T_v_dat_i : out std_logic_vector((v_mem_width-1) downto 0) |
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0) |
); |
end component; |
|
component wb_out_reg |
generic ( |
width : positive := 8; |
bus_width: positive := 8; |
offset: integer := 0 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic; |
rst_val: std_logic_vector(width-1 downto 0) := (others => '0'); |
|
cyc_i: in std_logic := '1'; |
stb_i: in std_logic; |
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1'); |
we_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0'); |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
q: out std_logic_vector (width-1 downto 0) |
); |
end component; |
|
signal total_stb: std_logic; |
signal ofs_stb: std_logic; |
signal reg_bank_stb: std_logic; |
signal ws_stb: std_logic; |
signal wait_state: std_logic_vector(3 downto 0); |
|
signal v_adr_o: std_logic_vector (v_adr_width-1 downto 0); |
signal v_sel_o: std_logic_vector ((v_dat_width/8)-1 downto 0); |
signal v_dat_i: std_logic_vector (v_dat_width-1 downto 0); |
signal v_dat_o: std_logic_vector (v_dat_width-1 downto 0); |
signal v_cyc_o: std_logic; |
signal v_ack_i: std_logic; |
signal v_we_o: std_logic; |
signal v_stb_o: std_logic; |
|
signal s_byen : std_logic_vector((v_dat_width/8)-1 downto 0); |
|
signal ws_dat_o: std_logic_vector(cpu_dat_width-1 downto 0); |
signal ws_ack_o: std_logic; |
|
signal s_wrn: std_logic; |
begin |
Core : vga_core |
ws_reg: wb_out_reg |
generic map( width => 4, bus_width => cpu_dat_width , offset => 0 ) |
port map( |
stb_i => ws_stb, |
q => wait_state, |
rst_val => "1111", |
dat_oi => dat_oi, |
dat_o => ws_dat_o, |
ack_oi => ack_oi, |
ack_o => ws_ack_o, |
adr_i => adr_i(0 downto 0), -- range should be calculated !!! |
sel_i => sel_i, cyc_i => cyc_i, we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
|
core : vga_core |
generic map ( |
v_dat_width => v_dat_width, |
v_adr_width => v_adr_width, |
cpu_dat_width => cpu_dat_width, |
cpu_adr_width => cpu_adr_width, |
fifo_size => fifo_size |
) |
port map ( |
clk_i => clk_i, |
clk_en => clk_en, |
rst_i => rst_i, |
dat_i => dat_i, |
dat_oi => dat_oi, |
dat_o => dat_o, |
-- CPU bus interface |
cyc_i => cyc_i, |
ack_o => ack_o, |
ack_oi => ack_oi, |
we_i => we_i, |
vmem_stb_i => vmem_stb_i, |
reg_stb_i => reg_stb_i, |
total_stb_i => total_stb, |
ofs_stb_i => ofs_stb, |
reg_bank_stb_i => reg_bank_stb, |
ack_o => ack_o, |
ack_oi => ws_ack_o, |
adr_i => adr_i, |
s_data => s_data, |
s_addr => s_addr, |
s_oen => s_oen, |
s_wrhn => s_wrhn, |
s_wrln => s_wrln, |
s_cen => s_cen, |
sel_i => sel_i, |
dat_i => dat_i, |
dat_oi => ws_dat_o, |
dat_o => dat_o, |
-- video memory interface |
v_adr_o => v_adr_o, |
v_sel_o => v_sel_o, |
v_dat_i => v_dat_i, |
v_dat_o => v_dat_o, |
v_cyc_o => v_cyc_o, |
v_ack_i => v_ack_i, |
v_we_o => v_we_o, |
v_stb_o => v_stb_o, |
|
h_sync => h_sync, |
h_blank => h_blank, |
v_sync => v_sync, |
139,14 → 258,61
h_tc => h_tc, |
v_tc => v_tc, |
blank => blank, |
video_out => video_out, |
video_out => video_out |
); |
|
T_v_we_o => T_v_we_o, |
T_v_stb_o => T_v_stb_o, |
T_v_ack_i => T_v_ack_i, |
T_v_adr_o => T_v_adr_o, |
T_v_sel_o => T_v_sel_o, |
T_v_dat_o => T_v_dat_o, |
T_v_dat_i => T_v_dat_i |
); |
mem_driver: wb_async_slave |
generic map (width => v_dat_width, addr_width => v_adr_width) |
port map ( |
clk_i => clk_i, |
rst_i => rst_i, |
|
wait_state => wait_state, |
|
adr_i => v_adr_o, |
sel_i => v_sel_o, |
dat_o => v_dat_i, |
dat_i => v_dat_o, |
-- dat_oi => (others => '0'), |
we_i => v_we_o, |
stb_i => v_stb_o, |
ack_o => v_ack_i, |
ack_oi => '0', |
|
a_data => s_data, |
a_addr => s_addr, |
a_rdn => s_oen, |
a_wrn => s_wrn, |
a_cen => s_cen, |
a_byen => s_byen |
); |
|
s_wrln <= s_wrn or s_byen(0); |
s_wrhn <= s_wrn or s_byen(1); |
|
|
addr_decoder: process is |
begin |
wait on reg_stb_i, adr_i; |
|
total_stb <= '0'; |
ofs_stb <= '0'; |
reg_bank_stb <= '0'; |
ws_stb <= '0'; |
|
if (reg_stb_i = '1') then |
case (adr_i(4)) is |
when '0' => |
case (adr_i(3 downto 2)) is |
when "00" => total_stb <= '1'; |
when "01" => ofs_stb <= '1'; |
when "10" => ws_stb <= '1'; |
when others => |
end case; |
when '1' => reg_bank_stb <= '1'; |
when others => |
end case; |
end if; |
end process; |
|
end vga_chip; |
/trunk/compile.sh
0,0 → 1,75
#!/bin/bash |
# |
# Script to compile sources to a library using Active HDL |
# (c) Copyright Andras Tantos <tantos@opencores.org> 2001/04/25 |
# This code is distributed under the terms and conditions of the GNU General Public Lince. |
# |
# USAGE: |
# |
# Set APATH to the installation directory of ActiveHDL and |
# LIB to whatever name your library has |
# RESULT_PATH to where generated files you wish to be put |
# Also make sure that you upadted the Library.cfg file to contain |
# the specified library name. |
# After the common part, list all files you wish to include in your library |
# with 'compile_file' preciding the file name. |
# |
# NOTES: |
# |
# This script depends on the following executables: |
# bash |
# cat |
# rm |
# mv |
# mkdir |
# echo |
# test |
# they are available under all UNIX-es and can be installed for windows |
# and DOS too. The windows version of these files can be obtained from |
# GNU Cygnus distribution (http://sources.redhat.com/cygwin) |
# The minimal package of these utilities are also available from |
# OpenCores web-site. |
|
APATH=C:/CAED/ActiveHDL.36/ |
LIB=wb_vga |
RESULT_PATH=ahdl |
|
# ___________Common part of the script____________ |
|
LIB_FILE=$RESULT_PATH/$LIB.lib |
CMP_FILE=$RESULT_PATH/0.mgf |
CMP=$APATH/bin/acombat.exe |
CMP_FLAGS="-avhdl $APATH -lib $LIB -93" |
|
compile_file() { |
LOG_FILE=$1 |
LOG_FILE=$RESULT_PATH/${LOG_FILE/.vhd/.rlt} |
ERR_FILE=${LOG_FILE/.rtl/.err} |
rm -f $LOG_FILE |
rm -f $ERR_FILE |
$CMP $CMP_FLAGS -log $LOG_FILE $1 || { |
mv $LOG_FILE $ERR_FILE |
cat $ERR_FILE |
exit 1 |
} |
cat $LOG_FILE |
} |
|
if test ! -d $RESULT_PATH; then |
mkdir $RESULT_PATH |
fi |
rm -f $RESULT_PATH/* |
if test ! -f $LIB_FILE; then |
echo > $LIB_FILE |
fi |
# ___________End of common part of the script____________ |
|
compile_file wb_io_reg.vhd |
compile_file mem_reader.vhd |
compile_file sync_gen.vhd |
compile_file hv_sync.vhd |
compile_file video_engine.vhd |
compile_file accel.vhd |
compile_file palette.vhd |
compile_file vga_core.vhd |
compile_file vga_chip.vhd |
/trunk/sync_gen.vhd
10,8 → 10,8
use IEEE.std_logic_1164.all; |
use IEEE.numeric_std.all; |
|
library work; |
use work.technology.all; |
library wb_tk; |
use wb_tk.technology.all; |
|
entity sync_gen is |
port ( |
/trunk/vga_core.vhd
8,17 → 8,21
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library work; |
--use wb_tk.all; |
use work.wb_tk.all; |
library wb_tk; |
use wb_tk.all; |
use wb_tk.technology.all; |
|
library wb_vga; |
use wb_vga.all; |
|
entity vga_core is |
generic ( |
-- cannot be overwritten at the moment... |
v_mem_width: positive := 16; |
fifo_size: positive := 256; |
v_addr_width : positive := 20; |
bus_width: positive := 8 |
v_dat_width: positive := 16; |
v_adr_width : positive := 20; |
cpu_dat_width: positive := 8; |
cpu_adr_width: positive := 21; |
fifo_size: positive := 256 |
); |
port ( |
clk_i: in std_logic; |
26,24 → 30,29
rst_i: in std_logic := '0'; |
|
-- CPU bus interface |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
cyc_i: in std_logic; |
we_i: in std_logic; |
vmem_stb_i: in std_logic; -- selects video memory |
total_stb_i: in std_logic; -- selects total register |
ofs_stb_i: in std_logic; -- selects offset register |
reg_bank_stb_i: in std_logic; -- selects all other registers (in a single bank) |
ack_o: out std_logic; |
ack_oi: in std_logic; |
we_i: in std_logic; |
vmem_stb_i: in std_logic; |
reg_stb_i: in std_logic; |
adr_i: in std_logic_vector (v_addr_width downto 0); |
adr_i: in std_logic_vector (v_adr_width downto 0); |
sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
|
-- video memory SRAM interface |
s_data : inout std_logic_vector((v_mem_width-1) downto 0); |
s_addr : out std_logic_vector((v_addr_width-1) downto 0); |
s_oen : out std_logic; |
s_wrhn : out std_logic; |
s_wrln : out std_logic; |
s_cen : out std_logic; |
-- video memory interface |
v_adr_o: out std_logic_vector (v_adr_width-1 downto 0); |
v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0); |
v_dat_i: in std_logic_vector (v_dat_width-1 downto 0); |
v_dat_o: out std_logic_vector (v_dat_width-1 downto 0); |
v_cyc_o: out std_logic; |
v_ack_i: in std_logic; |
v_we_o: out std_logic; |
v_stb_o: out std_logic; |
|
-- sync blank and video signal outputs |
h_sync: out std_logic; |
53,16 → 62,7
h_tc: out std_logic; |
v_tc: out std_logic; |
blank: out std_logic; |
video_out: out std_logic_vector (7 downto 0); -- video output binary signal (unused bits are forced to 0) |
|
-- TEST SIGNALS |
T_v_we_o: out std_logic; |
T_v_stb_o: out std_logic; |
T_v_ack_i: out std_logic; |
T_v_adr_o : out std_logic_vector((v_addr_width-1) downto 0); |
T_v_sel_o : out std_logic_vector((v_addr_width/8)-1 downto 0); |
T_v_dat_o : out std_logic_vector((v_mem_width-1) downto 0); |
T_v_dat_i : out std_logic_vector((v_mem_width-1) downto 0) |
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0) |
); |
end vga_core; |
|
113,40 → 113,6
); |
end component video_engine; |
|
component wb_async_slave |
generic ( |
width: positive := 16; |
addr_width: positive := 20 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- interface for wait-state generator state-machine |
wait_state: in std_logic_vector (3 downto 0); |
|
-- interface to wishbone master device |
adr_i: in std_logic_vector (addr_width-1 downto 0); |
sel_i: in std_logic_vector ((addr_width/8)-1 downto 0); |
dat_i: in std_logic_vector (width-1 downto 0); |
dat_o: out std_logic_vector (width-1 downto 0); |
dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-'); |
we_i: in std_logic; |
stb_i: in std_logic; |
ack_o: out std_logic := '0'; |
ack_oi: in std_logic := '-'; |
|
-- interface to async slave |
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z'); |
a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U'); |
a_rdn: out std_logic := '1'; |
a_wrn: out std_logic := '1'; |
a_cen: out std_logic := '1'; |
-- byte-enable signals |
a_byen: out std_logic_vector ((addr_width/8)-1 downto 0) |
); |
end component; |
|
component wb_arbiter |
port ( |
-- clk: in std_logic; |
190,32 → 156,36
end component; |
|
component wb_out_reg |
generic ( |
width : positive := 8; |
bus_width: positive := 8; |
offset: integer := 0 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic; |
rst_val: std_logic_vector(width-1 downto 0) := (others => '0'); |
generic ( |
width : positive := 8; |
bus_width: positive := 8; |
offset: integer := 0 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic; |
rst_val: std_logic_vector(width-1 downto 0) := (others => '0'); |
|
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
q: out std_logic_vector (width-1 downto 0); |
we_i: in std_logic; |
stb_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-' |
); |
cyc_i: in std_logic := '1'; |
stb_i: in std_logic; |
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1'); |
we_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0'); |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
q: out std_logic_vector (width-1 downto 0) |
); |
end component; |
|
component wb_bus_upsize |
component wb_bus_resize |
generic ( |
m_bus_width: positive := 8; -- master bus width |
m_addr_width: positive := 21; -- master bus width |
s_bus_width: positive := 16; -- slave bus width |
s_addr_width: positive := 20; -- master bus width |
little_endien: boolean := true -- if set to false, big endien |
); |
port ( |
239,7 → 209,7
m_stb_i: in std_logic; |
|
-- Slave bus interface |
s_adr_o: out std_logic_vector (m_addr_width-2 downto 0); |
s_adr_o: out std_logic_vector (s_addr_width-1 downto 0); |
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0); |
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0); |
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0); |
252,108 → 222,54
); |
end component; |
|
signal reset_core: std_logic_vector(0 downto 0); |
signal total: std_logic_vector(v_addr_width-1 downto 0); |
signal fifo_treshold: std_logic_vector(7 downto 0); |
signal bpp: std_logic_vector(1 downto 0); |
signal multi_scan: std_logic_vector(1 downto 0); |
signal hbs: std_logic_vector(7 downto 0); |
signal hss: std_logic_vector(7 downto 0); |
signal hse: std_logic_vector(7 downto 0); |
signal htotal: std_logic_vector(7 downto 0); |
signal vbs: std_logic_vector(7 downto 0); |
signal vss: std_logic_vector(7 downto 0); |
signal vse: std_logic_vector(7 downto 0); |
signal vtotal: std_logic_vector(7 downto 0); |
signal pps: std_logic_vector(7 downto 0); |
signal wait_state: std_logic_vector (3 downto 0); |
signal sync_pol: std_logic_vector (3 downto 0); |
signal total: std_logic_vector(v_adr_width-1 downto 0); |
signal offset: std_logic_vector(v_adr_width-1 downto 0); |
|
signal reg_bank: std_logic_vector((8*12)-1 downto 0); |
|
signal reset_core_do: std_logic_vector(bus_width-1 downto 0); |
signal total0_do: std_logic_vector(bus_width-1 downto 0); |
signal total1_do: std_logic_vector(bus_width-1 downto 0); |
signal total2_do: std_logic_vector(bus_width-1 downto 0); |
signal fifo_treshold_do: std_logic_vector(bus_width-1 downto 0); |
signal bpp_do: std_logic_vector(bus_width-1 downto 0); |
signal multi_scan_do: std_logic_vector(bus_width-1 downto 0); |
signal hbs_do: std_logic_vector(bus_width-1 downto 0); |
signal hss_do: std_logic_vector(bus_width-1 downto 0); |
signal hse_do: std_logic_vector(bus_width-1 downto 0); |
signal htotal_do: std_logic_vector(bus_width-1 downto 0); |
signal vbs_do: std_logic_vector(bus_width-1 downto 0); |
signal vss_do: std_logic_vector(bus_width-1 downto 0); |
signal vse_do: std_logic_vector(bus_width-1 downto 0); |
signal vtotal_do: std_logic_vector(bus_width-1 downto 0); |
signal pps_do: std_logic_vector(bus_width-1 downto 0); |
signal wait_state_do: std_logic_vector(bus_width-1 downto 0); |
signal vm_do: std_logic_vector(bus_width-1 downto 0); |
alias fifo_treshold: std_logic_vector(7 downto 0) is reg_bank( 7 downto 0); |
alias bpp: std_logic_vector(1 downto 0) is reg_bank( 9 downto 8); |
alias multi_scan: std_logic_vector(1 downto 0) is reg_bank(13 downto 12); |
alias hbs: std_logic_vector(7 downto 0) is reg_bank(23 downto 16); |
alias hss: std_logic_vector(7 downto 0) is reg_bank(31 downto 24); |
alias hse: std_logic_vector(7 downto 0) is reg_bank(39 downto 32); |
alias htotal: std_logic_vector(7 downto 0) is reg_bank(47 downto 40); |
alias vbs: std_logic_vector(7 downto 0) is reg_bank(55 downto 48); |
alias vss: std_logic_vector(7 downto 0) is reg_bank(63 downto 56); |
alias vse: std_logic_vector(7 downto 0) is reg_bank(71 downto 64); |
alias vtotal: std_logic_vector(7 downto 0) is reg_bank(79 downto 72); |
alias pps: std_logic_vector(7 downto 0) is reg_bank(87 downto 80); |
alias sync_pol: std_logic_vector (3 downto 0) is reg_bank(91 downto 88); |
alias reset_core: std_logic_vector(0 downto 0) is reg_bank(95 downto 95); |
|
signal reset_core_sel: std_logic; |
signal total0_sel: std_logic; |
signal total1_sel: std_logic; |
signal total2_sel: std_logic; |
signal fifo_treshold_sel: std_logic; |
signal bpp_sel: std_logic; |
signal multi_scan_sel: std_logic; |
signal hbs_sel: std_logic; |
signal hss_sel: std_logic; |
signal hse_sel: std_logic; |
signal htotal_sel: std_logic; |
signal vbs_sel: std_logic; |
signal vss_sel: std_logic; |
signal vse_sel: std_logic; |
signal vtotal_sel: std_logic; |
signal pps_sel: std_logic; |
signal wait_state_sel: std_logic; |
signal sync_pol_sel: std_logic; |
signal reg_bank_do: std_logic_vector(cpu_dat_width-1 downto 0); |
signal total_do: std_logic_vector(cpu_dat_width-1 downto 0); |
signal ofs_do: std_logic_vector(cpu_dat_width-1 downto 0); |
signal vm_do: std_logic_vector(cpu_dat_width-1 downto 0); |
|
signal reset_core_ack: std_logic; |
signal total0_ack: std_logic; |
signal total1_ack: std_logic; |
signal total2_ack: std_logic; |
signal fifo_treshold_ack: std_logic; |
signal bpp_ack: std_logic; |
signal multi_scan_ack: std_logic; |
signal hbs_ack: std_logic; |
signal hss_ack: std_logic; |
signal hse_ack: std_logic; |
signal htotal_ack: std_logic; |
signal vbs_ack: std_logic; |
signal vss_ack: std_logic; |
signal vse_ack: std_logic; |
signal vtotal_ack: std_logic; |
signal pps_ack: std_logic; |
signal wait_state_ack: std_logic; |
signal reg_bank_ack: std_logic; |
signal total_ack: std_logic; |
signal ofs_ack: std_logic; |
signal vm_ack: std_logic; |
|
signal a_adr_o : std_logic_vector((v_addr_width-1) downto 0); |
signal a_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0); |
signal a_dat_o : std_logic_vector((v_mem_width-1) downto 0); |
signal a_dat_i : std_logic_vector((v_mem_width-1) downto 0); |
signal a_adr_o : std_logic_vector((v_adr_width-1) downto 0); |
signal a_sel_o : std_logic_vector((v_adr_width/8)-1 downto 0); |
signal a_dat_o : std_logic_vector((v_dat_width-1) downto 0); |
signal a_dat_i : std_logic_vector((v_dat_width-1) downto 0); |
signal a_we_o : std_logic; |
signal a_stb_o : std_logic; |
signal a_cyc_o : std_logic; |
signal a_ack_i : std_logic; |
|
signal b_adr_o : std_logic_vector((v_addr_width-1) downto 0); |
signal b_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0); |
-- signal b_dat_o : std_logic_vector((v_mem_width-1) downto 0); |
signal b_dat_i : std_logic_vector((v_mem_width-1) downto 0); |
signal b_adr_o : std_logic_vector((v_adr_width-1) downto 0); |
signal b_sel_o : std_logic_vector((v_adr_width/8)-1 downto 0); |
-- signal b_dat_o : std_logic_vector((v_dat_width-1) downto 0); |
signal b_dat_i : std_logic_vector((v_dat_width-1) downto 0); |
signal b_stb_o : std_logic; |
-- signal b_we_o : std_logic; |
-- signal b_cyc_o : std_logic; |
signal b_ack_i : std_logic; |
|
signal v_we_o: std_logic; |
signal v_stb_o: std_logic; |
signal v_ack_i: std_logic; |
signal v_adr_o : std_logic_vector((v_addr_width-1) downto 0); |
signal v_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0); |
signal v_dat_o : std_logic_vector((v_mem_width-1) downto 0); |
signal v_dat_i : std_logic_vector((v_mem_width-1) downto 0); |
|
signal s_byen : std_logic_vector((v_addr_width/8)-1 downto 0); |
|
signal mux_signal: std_logic; |
|
signal high_prior: std_logic; |
366,212 → 282,54
signal i_v_blank: std_logic; |
|
signal s_wrn : std_logic; |
|
|
constant v_adr_zero : std_logic_vector(v_adr_width-1 downto 0) := (others => '0'); |
constant reg_bank_rst_val: std_logic_vector(reg_bank'Range) := (others => '0'); |
begin |
-- map all registers: |
reset_core_reg: wb_out_reg |
generic map( width => 1, bus_width => bus_width , offset => 4 ) |
-- adr_i: in std_logic_vector (max(log2((width+offset+bus_width-1)/bus_width)-1,0) downto 0) := (others => '0'); |
|
reg_bank_reg: wb_out_reg |
generic map( width => reg_bank'HIGH+1, bus_width => cpu_dat_width , offset => 0 ) |
port map( |
stb_i => reset_core_sel, |
q => reset_core, |
rst_val => "1", |
stb_i => reg_bank_stb_i, |
q => reg_bank, |
rst_val => reg_bank_rst_val, |
dat_oi => vm_do, |
dat_o => reset_core_do, |
dat_o => reg_bank_do, |
ack_oi => vm_ack, |
ack_o => reset_core_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
total0_reg: wb_out_reg |
generic map( width => 8, bus_width => bus_width , offset => 0 ) |
ack_o => reg_bank_ack, |
adr_i => adr_i(3 downto 0), -- range should be calculated !!! |
sel_i => sel_i, cyc_i => cyc_i, we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
ofs_reg: wb_out_reg |
generic map( width => v_adr_width, bus_width => cpu_dat_width , offset => 0 ) |
port map( |
stb_i => total0_sel, |
q => total(7 downto 0), |
rst_val => "00000000", |
dat_oi => reset_core_do, |
dat_o => total0_do, |
ack_oi => reset_core_ack, |
ack_o => total0_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
total1_reg: wb_out_reg |
generic map( width => 8, bus_width => bus_width , offset => 0 ) |
stb_i => ofs_stb_i, |
q => offset, |
rst_val => v_adr_zero, |
dat_oi => reg_bank_do, |
dat_o => ofs_do, |
ack_oi => reg_bank_ack, |
ack_o => ofs_ack, |
adr_i => adr_i(1 downto 0), -- range should be calculated !!! |
sel_i => sel_i, cyc_i => cyc_i, we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
total_reg: wb_out_reg |
generic map( width => v_adr_width, bus_width => cpu_dat_width , offset => 0 ) |
port map( |
stb_i => total1_sel, |
q => total(15 downto 8), |
rst_val => "00000000", |
dat_oi => total0_do, |
dat_o => total1_do, |
ack_oi => total0_ack, |
ack_o => total1_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
total2_reg: wb_out_reg |
generic map( width => 4, bus_width => bus_width , offset => 0 ) |
port map( |
stb_i => total2_sel, |
q => total(19 downto 16), |
rst_val => "0000", |
dat_oi => total1_do, |
dat_o => total2_do, |
ack_oi => total1_ack, |
ack_o => total2_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
fifo_treshold_reg: wb_out_reg |
generic map( width => 8, bus_width => bus_width , offset => 0 ) |
port map( |
stb_i => fifo_treshold_sel, |
q => fifo_treshold, |
rst_val => "00000000", |
dat_oi => total2_do, |
dat_o => fifo_treshold_do, |
ack_oi => total2_ack, |
ack_o => fifo_treshold_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
bpp_reg: wb_out_reg |
generic map( width => 2, bus_width => bus_width , offset => 0 ) |
port map( |
stb_i => bpp_sel, |
q => bpp, |
rst_val => "00", |
dat_oi => fifo_treshold_do, |
dat_o => bpp_do, |
ack_oi => fifo_treshold_ack, |
ack_o => bpp_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
multi_scan_reg: wb_out_reg |
generic map( width => 2, bus_width => bus_width , offset => 2 ) |
port map( |
stb_i => multi_scan_sel, |
q => multi_scan, |
rst_val => "00", |
dat_oi => bpp_do, |
dat_o => multi_scan_do, |
ack_oi => bpp_ack, |
ack_o => multi_scan_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
hbs_reg: wb_out_reg |
generic map( width => 8, bus_width => bus_width , offset => 0 ) |
port map( |
stb_i => hbs_sel, |
q => hbs, |
rst_val => "00000000", |
dat_oi => multi_scan_do, |
dat_o => hbs_do, |
ack_oi => multi_scan_ack, |
ack_o => hbs_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
hss_reg: wb_out_reg |
generic map( width => 8, bus_width => bus_width , offset => 0 ) |
port map( |
stb_i => hss_sel, |
q => hss, |
rst_val => "00000000", |
dat_oi => hbs_do, |
dat_o => hss_do, |
ack_oi => hbs_ack, |
ack_o => hss_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
hse_reg: wb_out_reg |
generic map( width => 8, bus_width => bus_width , offset => 0 ) |
port map( |
stb_i => hse_sel, |
q => hse, |
rst_val => "00000000", |
dat_oi => hss_do, |
dat_o => hse_do, |
ack_oi => hss_ack, |
ack_o => hse_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
htotal_reg: wb_out_reg |
generic map( width => 8, bus_width => bus_width , offset => 0 ) |
port map( |
stb_i => htotal_sel, |
q => htotal, |
rst_val => "00000000", |
dat_oi => hse_do, |
dat_o => htotal_do, |
ack_oi => hse_ack, |
ack_o => htotal_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
vbs_reg: wb_out_reg |
generic map( width => 8, bus_width => bus_width , offset => 0 ) |
port map( |
stb_i => vbs_sel, |
q => vbs, |
rst_val => "00000000", |
dat_oi => htotal_do, |
dat_o => vbs_do, |
ack_oi => htotal_ack, |
ack_o => vbs_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
vss_reg: wb_out_reg |
generic map( width => 8, bus_width => bus_width , offset => 0 ) |
port map( |
stb_i => vss_sel, |
q => vss, |
rst_val => "00000000", |
dat_oi => vbs_do, |
dat_o => vss_do, |
ack_oi => vbs_ack, |
ack_o => vss_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
vse_reg: wb_out_reg |
generic map( width => 8, bus_width => bus_width , offset => 0 ) |
port map( |
stb_i => vse_sel, |
q => vse, |
rst_val => "00000000", |
dat_oi => vss_do, |
dat_o => vse_do, |
ack_oi => vss_ack, |
ack_o => vse_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
vtotal_reg: wb_out_reg |
generic map( width => 8, bus_width => bus_width , offset => 0 ) |
port map( |
stb_i => vtotal_sel, |
q => vtotal, |
rst_val => "00000000", |
dat_oi => vse_do, |
dat_o => vtotal_do, |
ack_oi => vse_ack, |
ack_o => vtotal_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
pps_reg: wb_out_reg |
generic map( width => 8, bus_width => bus_width , offset => 0 ) |
port map( |
stb_i => pps_sel, |
q => pps, |
rst_val => "00000000", |
dat_oi => vtotal_do, |
dat_o => pps_do, |
ack_oi => vtotal_ack, |
ack_o => pps_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
wait_state_reg: wb_out_reg |
generic map( width => 4, bus_width => bus_width , offset => 0 ) |
port map( |
stb_i => wait_state_sel, |
q => wait_state, |
rst_val => "0000", |
dat_oi => pps_do, |
dat_o => wait_state_do, |
ack_oi => pps_ack, |
ack_o => wait_state_ack, |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
sync_pol_reg: wb_out_reg |
generic map( width => 4, bus_width => bus_width , offset => 4 ) |
port map( |
stb_i => sync_pol_sel, |
q => sync_pol, |
rst_val => "0000", |
dat_oi => wait_state_do, |
stb_i => total_stb_i, |
q => total, |
rst_val => v_adr_zero, |
dat_oi => ofs_do, |
dat_o => dat_o, -- END OF THE CHAIN |
ack_oi => wait_state_ack, |
ack_oi => ofs_ack, |
ack_o => ack_o, -- END OF THE CHAIN |
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
adr_i => adr_i(1 downto 0), -- range should be calculated !!! |
sel_i => sel_i, cyc_i => cyc_i, we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
|
reset_engine <= rst_i or reset_core(0); |
reset_engine <= rst_i or not reset_core(0); |
|
v_e: video_engine |
generic map ( v_mem_width => v_mem_width, v_addr_width => v_addr_width, fifo_size => fifo_size, dual_scan_fifo_size => fifo_size ) |
generic map ( v_mem_width => v_dat_width, v_addr_width => v_adr_width, fifo_size => fifo_size, dual_scan_fifo_size => fifo_size ) |
port map ( |
clk => clk_i, |
clk_en => clk_en, |
612,16 → 370,16
h_blank <= i_h_blank;-- xor sync_pol(2); |
v_blank <= i_v_blank;-- xor sync_pol(3); |
|
resize: wb_bus_upsize |
resize: wb_bus_resize |
generic map ( |
m_bus_width => bus_width, s_bus_width => v_mem_width, m_addr_width => v_addr_width+1 |
m_bus_width => cpu_dat_width, s_bus_width => v_dat_width, m_addr_width => cpu_adr_width |
) |
port map ( |
m_adr_i => adr_i, |
-- m_sel_i => (others => '1'), |
m_cyc_i => cyc_i, |
m_sel_i => sel_i, |
m_dat_i => dat_i, |
m_dat_oi => dat_oi, -- Beginning of the chain |
m_cyc_i => cyc_i, |
m_dat_o => vm_do, |
m_ack_o => vm_ack, |
m_ack_oi => ack_oi, -- Beginning of the chain |
653,11 → 411,12
b_cyc_i => b_stb_o, |
b_stb_i => b_stb_o, |
b_ack_o => b_ack_i, |
b_ack_oi => '0', -- maybe not needed at all |
b_ack_oi => '0', |
|
s_we_o => v_we_o, |
s_stb_o => v_stb_o, |
s_ack_i => v_ack_i, |
s_cyc_o => v_cyc_o, |
|
mux_signal => mux_signal, |
|
684,91 → 443,5
end if; |
end process; |
|
mem_driver: wb_async_slave |
generic map (width => v_mem_width, addr_width => v_addr_width) |
port map ( |
clk_i => clk_i, |
rst_i => reset_engine, |
|
wait_state => wait_state, |
|
adr_i => v_adr_o, |
sel_i => v_sel_o, |
dat_o => v_dat_i, |
dat_i => v_dat_o, |
-- dat_oi => (others => '0'), -- may not be needed |
we_i => v_we_o, |
stb_i => v_stb_o, |
ack_o => v_ack_i, |
ack_oi => '0', -- may not be needed |
|
a_data => s_data, |
a_addr => s_addr, |
a_rdn => s_oen, |
a_wrn => s_wrn, |
a_cen => s_cen, |
a_byen => s_byen |
); |
|
s_wrln <= s_wrn or s_byen(0); |
s_wrhn <= s_wrn or s_byen(1); |
|
addr_decoder: process is |
begin |
wait on reg_stb_i, adr_i; |
|
reset_core_sel <= '0'; |
total0_sel <= '0'; |
total1_sel <= '0'; |
total2_sel <= '0'; |
fifo_treshold_sel <= '0'; |
bpp_sel <= '0'; |
multi_scan_sel <= '0'; |
hbs_sel <= '0'; |
hss_sel <= '0'; |
hse_sel <= '0'; |
htotal_sel <= '0'; |
vbs_sel <= '0'; |
vss_sel <= '0'; |
vse_sel <= '0'; |
vtotal_sel <= '0'; |
pps_sel <= '0'; |
wait_state_sel <= '0'; |
sync_pol_sel <= '0'; |
|
if (reg_stb_i = '1') then |
case (adr_i(4 downto 0)) is |
when "00000" => total0_sel <= '1'; |
when "00001" => total1_sel <= '1'; |
when "00010" => total2_sel <= '1'; |
when "00011" => fifo_treshold_sel <= '1'; |
|
when "00100" => hbs_sel <= '1'; |
when "00101" => hss_sel <= '1'; |
when "00110" => hse_sel <= '1'; |
when "00111" => htotal_sel <= '1'; |
|
when "01000" => vbs_sel <= '1'; |
when "01001" => vss_sel <= '1'; |
when "01010" => vse_sel <= '1'; |
when "01011" => vtotal_sel <= '1'; |
|
when "01100" => pps_sel <= '1'; |
when "01101" => wait_state_sel <= '1'; sync_pol_sel <= '1'; |
when "01110" => bpp_sel <= '1'; multi_scan_sel <= '1'; reset_core_sel <= '1'; |
when others => |
end case; |
end if; |
end process; |
|
-- TEST SIGNALS |
T_v_we_o <= v_we_o; |
T_v_stb_o <= v_stb_o; |
T_v_ack_i <= v_ack_i; |
T_v_adr_o <= v_adr_o; |
T_v_sel_o <= v_sel_o; |
T_v_dat_o <= v_dat_o; |
T_v_dat_i <= v_dat_i; |
|
end vga_core; |
|
/trunk/accel.vhd
0,0 → 1,224
-- |
-- Address generator and accelerator. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
|
|
-- Standard library. |
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.numeric_std.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
use wb_tk.all; |
|
library wb_vga; |
use wb_vga.all; |
|
entity accel is |
generic ( |
accel_size: positive := 9; |
video_addr_width: positive := 20; |
video_data_width: positive := 16; |
data_width: positive := 16 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- Slave interface to the CPU side |
we_i: in std_logic; |
cyc_i: in std_logic; |
cur_stb_i: in std_logic; |
ext_stb_i: in std_logic; |
acc_stb_i: in std_logic; |
mem_stb_i: in std_logic; |
|
sel_i: in std_logic_vector ((data_width/8)-1 downto 0) := (others => '1'); |
adr_i: in std_logic_vector(accel_size-1 downto 0); |
dat_i: in std_logic_vector(data_width-1 downto 0); |
dat_o: out std_logic_vector(data_width-1 downto 0); |
dat_oi: in std_logic_vector(data_width-1 downto 0); |
|
ack_o: out std_logic; |
ack_oi: in std_logic; |
|
-- Master interface to the video memory side. |
v_we_o: out std_logic; |
v_cyc_o: out std_logic; |
v_sel_o: out std_logic; |
|
v_adr_o: out std_logic_vector (video_addr_width-1 downto 0); |
v_dat_o: out std_logic_vector (video_data_width-1 downto 0); |
v_dat_i: in std_logic_vector (video_data_width-1 downto 0); |
|
v_ack_i: in std_logic |
); |
end accel; |
|
architecture accel of accel is |
component wb_io_reg |
generic ( |
width : positive := video_addr_width; |
bus_width: positive := data_width; |
offset: integer := 0 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic; |
rst_val: std_logic_vector(width-1 downto 0) := (others => '0'); |
|
cyc_i: in std_logic := '1'; |
stb_i: in std_logic; |
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1'); |
we_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0'); |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
q: out std_logic_vector (width-1 downto 0); |
ext_d: in std_logic_vector (width-1 downto 0) := (others => '-'); |
ext_we: in std_logic := '0' |
); |
end component; |
|
component wb_ram |
generic ( |
data_width: positive := 8; |
addr_width: positive := 10 |
); |
port ( |
clk_i: in std_logic; |
adr_i: in std_logic_vector (addr_width-1 downto 0); |
dat_i: in std_logic_vector (data_width-1 downto 0); |
dat_oi: in std_logic_vector (data_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (data_width-1 downto 0); |
cyc_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
we_i: in std_logic; |
stb_i: in std_logic |
); |
end component; |
|
signal cursor: std_logic_vector(video_addr_width-1 downto 0); |
signal accel_ram_d_out: std_logic_vector(video_addr_width-1 downto 0); |
signal accel_ram_dat_i: std_logic_vector(video_addr_width-1 downto 0); |
signal accel_ram_stb: std_logic; |
signal accel_ram_ack: std_logic; |
signal accel_ram_we: std_logic; |
signal accel_ram_clk: std_logic; |
signal next_cur: std_logic_vector(video_addr_width-1 downto 0); |
signal cur_update: std_logic := '0'; |
signal mem_ack_o: std_logic := '1'; |
signal mem_dat_o: std_logic_vector(data_width-1 downto 0); |
signal cur_ack_o: std_logic := '1'; |
signal cur_dat_o: std_logic_vector(data_width-1 downto 0); |
signal ext_value: std_logic_vector(max(video_addr_width - data_width,1)-1 downto 0); |
signal ext_ext_we: std_logic; |
begin |
accel_ram_stb <= acc_stb_i or mem_stb_i; |
accel_ram_we <= we_i and acc_stb_i; |
accel_ram_clk <= clk_i; |
accel_ram_dat_i(min(video_addr_width,data_width)-1 downto 0) <= dat_i; |
high_accel_dat_gen: if (video_addr_width > data_width) generate |
accel_ram_dat_i(video_addr_width-1 downto data_width) <= ext_value; |
end generate; |
accel_ram: wb_ram |
generic map ( |
data_width => video_addr_width, |
addr_width => accel_size |
) |
port map ( |
clk_i => clk_i, |
cyc_i => cyc_i, |
stb_i => accel_ram_stb, |
we_i => accel_ram_we, |
adr_i => adr_i, |
dat_i => accel_ram_dat_i, |
dat_o => accel_ram_d_out, |
ack_o => accel_ram_ack |
); |
|
v_sel_o <= mem_stb_i; |
v_cyc_o <= mem_stb_i and cyc_i; |
v_adr_o <= cursor; |
v_we_o <= we_i; |
v_dat_o <= dat_i; |
|
next_cur <= cursor + accel_ram_d_out; |
|
ext_ext_we <= acc_stb_i and not we_i; |
ext_reg_gen: if (video_addr_width > data_width) generate |
ext_reg: wb_io_reg |
generic map ( |
width => video_addr_width - data_width, |
bus_width => data_width, |
offset => 0 |
) |
port map ( |
clk_i => clk_i, |
rst_i => rst_i, |
rst_val => (others => '0'), |
|
cyc_i => cyc_i, |
stb_i => ext_stb_i, |
sel_i => sel_i, |
we_i => we_i, |
ack_o => ack_o, |
ack_oi => cur_ack_o, |
adr_i => adr_i(size2bits((video_addr_width-1)/data_width)-1 downto 0), |
dat_i => dat_i, |
dat_oi => cur_dat_o, |
dat_o => dat_o, |
q => ext_value, |
ext_d => accel_ram_d_out(video_addr_width-1 downto data_width), |
ext_we => ext_ext_we |
); |
end generate; |
ext_gen: if (video_addr_width <= data_width) generate |
dat_o <= cur_dat_o; |
ack_o <= cur_ack_o; |
ext_value(0) <= '0'; |
end generate; |
|
cur_reg: wb_io_reg |
port map ( |
clk_i => clk_i, |
rst_i => rst_i, |
rst_val => (others => '0'), |
|
cyc_i => cyc_i, |
stb_i => cur_stb_i, |
sel_i => sel_i, |
we_i => we_i, |
ack_o => cur_ack_o, |
ack_oi => mem_ack_o, |
adr_i => adr_i(size2bits((video_addr_width+data_width-1)/data_width)-1 downto 0), |
dat_i => dat_i, |
dat_oi => mem_dat_o, |
dat_o => cur_dat_o, |
q => cursor, |
ext_d => next_cur, |
ext_we => cur_update |
); |
|
cur_update <= mem_stb_i and cyc_i and v_ack_i; |
|
gen_dat_o: for i in dat_o'RANGE generate |
mem_dat_o(i) <= ( |
(cyc_i and ((accel_ram_d_out(i) and acc_stb_i) or (v_dat_i(i) and mem_stb_i))) or |
(dat_oi(i) and ((not (acc_stb_i or mem_stb_i or cur_stb_i)) or (not cyc_i))) |
); |
end generate; |
mem_ack_o <= ( |
(cyc_i and ((accel_ram_ack and acc_stb_i) or (v_ack_i and mem_stb_i))) or |
(ack_oi and ((not (acc_stb_i or mem_stb_i or cur_stb_i)) or (not cyc_i))) |
); |
|
end accel; |
/trunk/video_engine.vhd
8,8 → 8,8
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library work; |
use work.technology.all; |
library wb_tk; |
use wb_tk.technology.all; |
|
entity video_engine is |
generic ( |
/trunk/wb_io_reg.vhd
0,0 → 1,104
-- |
-- Wishbone bus toolkit. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
-- |
-- ELEMENTS: |
-- wb_io_reg: A slightly modified version of the wb_out_reg component |
|
------------------------------------------------------------------------------- |
-- |
-- wb_io_reg. A slightly modified version of the wb_out_reg component |
-- |
------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.STD_LOGIC_UNSIGNED.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
|
entity wb_io_reg is |
generic ( |
width : positive := 8; |
bus_width: positive := 8; |
offset: integer := 0 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic; |
rst_val: std_logic_vector(width-1 downto 0) := (others => '0'); |
|
cyc_i: in std_logic := '1'; |
stb_i: in std_logic; |
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1'); |
we_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0'); |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
q: out std_logic_vector (width-1 downto 0); |
ext_d: in std_logic_vector (width-1 downto 0) := (others => '-'); |
ext_we: in std_logic := '0' |
); |
end wb_io_reg; |
|
architecture wb_io_reg of wb_io_reg is |
signal content : std_logic_vector (width-1 downto 0); |
begin |
-- output bus handling with logic |
gen_dat_o: process is |
variable rd_sel: std_logic; |
variable adr: integer; |
variable reg_i: integer; |
begin |
wait on dat_oi, we_i, stb_i, content, adr_i, cyc_i, sel_i; |
rd_sel := cyc_i and stb_i and not we_i; |
for i in dat_i'RANGE loop |
adr := CONV_INTEGER(adr_i); |
reg_i := i-offset+adr*bus_width; |
if ((reg_i >= 0) and (reg_i < width) and (sel_i(i/8) = '1')) then |
dat_o(i) <= (dat_oi(i) and not rd_sel) or (content(reg_i) and rd_sel); |
else |
dat_o(i) <= dat_oi(i); |
end if; |
end loop; |
end process; |
|
-- this item never generates any wait-states unless an external write is under process |
-- ack_o <= (stb_i or ack_oi) and (not (ext_we and we_i)); |
ack_o <= (ack_oi and not stb_i) or ((not (ext_we and we_i)) and stb_i); |
-- ack_o <= (stb_i or ack_oi); |
|
reg: process is |
variable adr: integer; |
variable reg_i: integer; |
begin |
wait until clk_i'EVENT and clk_i='1'; |
if (rst_i = '1') then |
content <= rst_val; |
else |
if (ext_we = '1') then |
content <= ext_d; |
else |
if (stb_i = '1' and cyc_i = '1' and we_i = '1') then |
for i in dat_i'RANGE loop |
adr := CONV_INTEGER(adr_i); |
reg_i := i-offset+adr*bus_width; |
if ((reg_i >= 0) and (reg_i < width) and (sel_i(i/8) = '1')) then |
content(reg_i) <= dat_i(i); |
end if; |
end loop; |
end if; |
end if; |
end if; |
end process; |
q <= content; |
end wb_io_reg; |
|
|
/trunk/Makefile
0,0 → 1,2
all: |
bash compile.sh |
/trunk/palette.vhd
0,0 → 1,168
-- |
-- Palette RAM. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
|
------------------------------------------------------------------------------- |
-- |
-- wb_pal_ram |
-- |
------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
use wb_tk.all; |
|
entity wb_pal_ram is |
generic ( |
cpu_dat_width: positive := 8; |
cpu_adr_width: positive := 9; |
v_dat_width: positive := 16; |
v_adr_width: positive := 8 |
); |
port ( |
-- Wishbone interface to CPU (write-only support) |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
adr_i: in std_logic_vector (cpu_adr_width-1 downto 0); |
-- sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
cyc_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
err_o: out std_logic; |
err_oi: in std_logic := '-'; |
-- rty_o: out std_logic; |
-- rty_oi: in std_logic := '-'; |
we_i: in std_logic; |
stb_i: in std_logic; |
-- Interface to the video output |
blank: in std_logic; |
v_dat_i: in std_logic_vector(v_adr_width-1 downto 0); |
v_dat_o: out std_logic_vector(v_dat_width-1 downto 0) |
); |
end wb_pal_ram; |
|
architecture wb_pal_ram of wb_pal_ram is |
component dpram |
generic ( |
data_width : positive; |
addr_width : positive |
); |
port ( |
clk : in std_logic; |
|
r_d_out : out std_logic_vector(data_width-1 downto 0); |
r_rd : in std_logic; |
r_clk_en : in std_logic; |
r_addr : in std_logic_vector(addr_width-1 downto 0); |
|
w_d_in : in std_logic_vector(data_width-1 downto 0); |
w_wr : in std_logic; |
w_clk_en : in std_logic; |
w_addr : in std_logic_vector(addr_width-1 downto 0) |
); |
end component; |
|
component wb_out_reg |
generic ( |
width : positive := 8; |
bus_width: positive := 8; |
offset: integer := 0 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic; |
rst_val: std_logic_vector(width-1 downto 0) := (others => '0'); |
|
cyc_i: in std_logic := '1'; |
stb_i: in std_logic; |
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1'); |
we_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0'); |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
q: out std_logic_vector (width-1 downto 0) |
); |
end component; |
|
signal mem_we: std_logic; |
signal mem_rd: std_logic; |
signal mem_d_in: std_logic_vector(v_dat_width-1 downto 0); |
signal ext_reg_stb: std_logic; |
signal mem_stb: std_logic; |
signal mem_d_out: std_logic_vector(v_dat_width-1 downto 0); |
begin |
mem_stb_gen1: if (cpu_dat_width < v_dat_width) generate |
mem_stb <= '1' WHEN adr_i(cpu_adr_width-v_adr_width-1 downto 0)=(cpu_adr_width-v_adr_width-1 downto 0 =>'1') ELSE '0'; |
end generate; |
mem_stb_gen2: if (cpu_dat_width >= v_dat_width) generate |
mem_stb <= '1'; |
end generate; |
mem_we <= we_i and stb_i and cyc_i and mem_stb; |
mem_rd <= not blank; |
mem_d_in_gen1: if (cpu_dat_width < v_dat_width) generate |
mem_d_in(v_dat_width-1 downto v_dat_width-cpu_dat_width) <= dat_i; |
end generate; |
mem_d_in_gen2: if (cpu_dat_width >= v_dat_width) generate |
mem_d_in(v_dat_width-1 downto 0) <= dat_i(mem_d_in'RANGE); |
end generate; |
tech_ram: dpram |
generic map( |
data_width => v_dat_width, |
addr_width => v_adr_width |
) |
port map ( |
clk => clk_i, |
|
r_d_out => mem_d_out, |
r_rd => mem_rd, |
r_clk_en => '1', |
r_addr => v_dat_i, |
|
w_d_in => mem_d_in, |
w_wr => mem_we, |
w_clk_en => '1', |
w_addr => adr_i(cpu_adr_width-1 downto cpu_adr_width-v_adr_width) |
); |
v_dat_o_gen: for i in v_dat_o'RANGE generate |
v_dat_o(i) <= mem_d_out(i) and not blank; |
end generate; |
|
ext_reg_stb <= we_i and stb_i and cyc_i and not mem_stb; |
ext_reg_gen: if (cpu_dat_width < v_dat_width) generate |
ext_reg: wb_out_reg |
generic map ( |
width => v_dat_width-cpu_dat_width, |
bus_width => cpu_dat_width, |
offset => 0 |
) |
port map ( |
clk_i => clk_i, |
rst_i => rst_i, |
|
cyc_i => cyc_i, |
stb_i => ext_reg_stb, |
we_i => we_i, |
-- ack_o |
adr_i => adr_i(cpu_adr_width-v_adr_width-1 downto 0), |
dat_i => dat_i, |
q => mem_d_in(v_dat_width-cpu_dat_width-1 downto 0) |
); |
end generate; |
|
dat_o <= dat_oi; |
ack_o <= ( we_i and (stb_i and cyc_i)) or (ack_oi and not (stb_i and cyc_i)); |
err_o <= ((not we_i) and (stb_i and cyc_i)) or (err_oi and not (stb_i and cyc_i)); |
end wb_pal_ram; |
|