URL
https://opencores.org/ocsvn/wb_vga/wb_vga/trunk
Subversion Repositories wb_vga
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Rev 7 → Rev 8
/tags/a01/vga_core.vhd
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/tags/a01/sync_gen.vhd
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/tags/a01/wb_tk.vhd
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/tags/a01/hv_sync.vhd
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/tags/a01/technology.vhd
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/tags/a01/video_engine.vhd
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/tags/a01/TestBench/vga_chip_TB.vhd
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/tags/a01/gpl.txt
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/tags/a01/mem_reader.vhd
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/tags/a01/vga_chip.vhd
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/trunk/technology.vhd
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/trunk/vga_chip.vhd
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/trunk/gpl.txt
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/trunk/compile.sh
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/trunk/vga_core.vhd
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/trunk/wb_tk/wb_test.vhd
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/trunk/wb_tk/wb_ram.vhd
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/trunk/wb_tk/technology.vhd
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/trunk/wb_tk/wb_out_reg.vhd
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/trunk/wb_tk/wb_bus_dnsize.vhd
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/trunk/wb_tk/Makefile
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/trunk/wb_tk/TestBench/wb_out_reg_TB.vhd
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/trunk/wb_tk/TestBench/wb_bus_dnsize_TB.vhd
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/trunk/wb_tk/wb_async_slave.vhd
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/trunk/wb_tk/wb_bus_upsize.vhd
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/trunk/wb_tk/wb_arbiter.vhd
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/trunk/wb_tk/gpl.txt
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/trunk/wb_tk/wb_async_master.vhd
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/trunk/wb_tk/compile.sh
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/trunk/wb_tk/wb_bus_resize.vhd
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/trunk/wb_tk/wb_tk.vhd
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/trunk/video_engine.vhd
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/trunk/vga_core_v2.vhd
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/trunk/wb_io_reg.vhd
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/trunk/Makefile
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/trunk/palette.vhd
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/trunk/TestBench/accel_TB.vhd
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/trunk/TestBench/vga_core_v2_TB.vhd
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/trunk/TestBench/palette_TB.vhd
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/trunk/TestBench/vga_chip_TB.vhd
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/trunk/mem_reader.vhd
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/trunk/sync_gen.vhd
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/trunk/accel.vhd
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/trunk/hv_sync.vhd
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/wb_vga/trunk/wb_tk/TestBench/wb_out_reg_TB.vhd
0,0 → 1,279
-- |
-- A test bench for 32-bit access |
-- |
|
library ieee,wb_tk; |
use ieee.std_logic_1164.all; |
use wb_tk.technology.all; |
use wb_tk.wb_test.all; |
|
entity wb_out_reg_tb_32 is |
-- Generic declarations of the tested unit |
generic( |
width : POSITIVE := 16; |
bus_width : POSITIVE := 32; |
offset : INTEGER := 4 ); |
end wb_out_reg_tb_32; |
|
architecture TB of wb_out_reg_tb_32 is |
-- Component declaration of the tested unit |
component wb_out_reg |
generic( |
width : POSITIVE := width; |
bus_width : POSITIVE := bus_width; |
offset : INTEGER := offset ); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic; |
rst_val: std_logic_vector(width-1 downto 0) := (others => '0'); |
|
cyc_i: in std_logic := '1'; |
stb_i: in std_logic; |
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1'); |
we_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0'); |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
q: out std_logic_vector (width-1 downto 0) |
); |
end component; |
|
-- Stimulus signals - signals mapped to the input and inout ports of tested entity |
signal adr_i : std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0'); |
signal clk_i : std_logic; |
signal rst_i : std_logic; |
signal rst_val : std_logic_vector((width-1) downto 0) := (others => '0'); |
signal cyc_i : std_logic; |
signal stb_i : std_logic; |
signal sel_i : std_logic_vector(((bus_width/8)-1) downto 0) := (others => '1'); |
signal we_i : std_logic; |
signal ack_oi : std_logic; |
signal dat_i : std_logic_vector((bus_width-1) downto 0); |
signal dat_oi : std_logic_vector((bus_width-1) downto 0); |
-- Observed signals - signals mapped to the output ports of tested entity |
signal ack_o : std_logic; |
signal dat_o : std_logic_vector((bus_width-1) downto 0); |
signal q : std_logic_vector((width-1) downto 0); |
|
-- Add your code here ... |
|
begin |
rst_val <= (others => '0'); |
ack_oi <= 'U'; |
dat_oi <= (others => 'U'); |
|
-- Unit Under Test port map |
UUT : wb_out_reg |
port map |
(clk_i => clk_i, |
rst_i => rst_i, |
rst_val => rst_val, |
cyc_i => cyc_i, |
stb_i => stb_i, |
sel_i => sel_i, |
we_i => we_i, |
ack_o => ack_o, |
ack_oi => ack_oi, |
adr_i => adr_i, |
dat_i => dat_i, |
dat_oi => dat_oi, |
dat_o => dat_o, |
q => q ); |
|
clk: process is |
begin |
clk_i <= '0'; |
wait for 25ns; |
clk_i <= '1'; |
wait for 25ns; |
end process; |
|
reset: process is |
begin |
rst_i <= '1'; |
wait for 150ns; |
rst_i <= '0'; |
wait; |
end process; |
|
master: process is |
begin |
we_i <= '0'; |
cyc_i <= '0'; |
stb_i <= '0'; |
adr_i <= (others => '0'); |
dat_i <= (others => '0'); |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","00000000000000000000000000000000"); |
rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","00000000000000000000000000000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","11111111111111111111111111111111"); |
rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","11111111111111111111111111111111"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","01110110010101000011001000010000"); |
rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","01110110010101000011001000010000"); |
|
sel_i <= add_one(sel_i); |
-- if (sel_i = "1111") then wait; end if; |
end process; |
end TB; |
|
configuration TB_wb_out_reg_32 of wb_out_reg_tb_32 is |
for TB |
for UUT : wb_out_reg |
use entity work.wb_out_reg(wb_out_reg); |
end for; |
end for; |
end TB_wb_out_reg_32; |
|
|
|
-- |
-- A test bench for 16-bit access |
-- |
|
|
library ieee,wb_tk; |
use ieee.std_logic_1164.all; |
use wb_tk.technology.all; |
use wb_tk.wb_test.all; |
|
entity wb_out_reg_tb_16 is |
-- Generic declarations of the tested unit |
generic( |
width : POSITIVE := 16; |
bus_width : POSITIVE := 16; |
offset : INTEGER := 4 ); |
end wb_out_reg_tb_16; |
|
architecture TB of wb_out_reg_tb_16 is |
-- Component declaration of the tested unit |
component wb_out_reg |
generic( |
width : POSITIVE := width; |
bus_width : POSITIVE := bus_width; |
offset : INTEGER := offset ); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic; |
rst_val: std_logic_vector(width-1 downto 0) := (others => '0'); |
|
cyc_i: in std_logic := '1'; |
stb_i: in std_logic; |
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1'); |
we_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
adr_i: in std_logic_vector (max(log2((width+offset+bus_width-1)/bus_width)-1,0) downto 0) := (others => '0'); |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
q: out std_logic_vector (width-1 downto 0) |
); |
end component; |
|
signal adr_i : std_logic_vector (max(log2((width+offset+bus_width-1)/bus_width)-1,0) downto 0) := (others => '0'); |
-- Stimulus signals - signals mapped to the input and inout ports of tested entity |
signal clk_i : std_logic; |
signal rst_i : std_logic; |
signal rst_val : std_logic_vector((width-1) downto 0) := (others => '0'); |
signal cyc_i : std_logic; |
signal stb_i : std_logic; |
signal sel_i : std_logic_vector(((bus_width/8)-1) downto 0) := (others => '1'); |
signal we_i : std_logic; |
signal ack_oi : std_logic; |
signal dat_i : std_logic_vector((bus_width-1) downto 0); |
signal dat_oi : std_logic_vector((bus_width-1) downto 0); |
-- Observed signals - signals mapped to the output ports of tested entity |
signal ack_o : std_logic; |
signal dat_o : std_logic_vector((bus_width-1) downto 0); |
signal q : std_logic_vector((width-1) downto 0); |
|
-- Add your code here ... |
|
begin |
rst_val <= (others => '0'); |
ack_oi <= 'U'; |
dat_oi <= (others => 'U'); |
|
-- Unit Under Test port map |
UUT : wb_out_reg |
port map |
(clk_i => clk_i, |
rst_i => rst_i, |
rst_val => rst_val, |
cyc_i => cyc_i, |
stb_i => stb_i, |
sel_i => sel_i, |
we_i => we_i, |
ack_o => ack_o, |
ack_oi => ack_oi, |
adr_i => adr_i, |
dat_i => dat_i, |
dat_oi => dat_oi, |
dat_o => dat_o, |
q => q ); |
|
clk: process is |
begin |
clk_i <= '0'; |
wait for 25ns; |
clk_i <= '1'; |
wait for 25ns; |
end process; |
|
reset: process is |
begin |
rst_i <= '1'; |
wait for 150ns; |
rst_i <= '0'; |
wait; |
end process; |
|
master: process is |
begin |
we_i <= '0'; |
cyc_i <= '0'; |
stb_i <= '0'; |
adr_i <= (others => '0'); |
dat_i <= (others => '0'); |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","0000000000000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","0000000000000000"); |
rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","0000000000000000"); |
rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","0000000000000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","1111111111111111"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","1111111111111111"); |
rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","1111111111111111"); |
rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","1111111111111111"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","0111011001010100"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","0011001000010000"); |
rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","0111011001010100"); |
rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","0011001000010000"); |
|
sel_i <= add_one(sel_i); |
end process; |
end TB; |
|
configuration TB_wb_out_reg_16 of wb_out_reg_tb_16 is |
for TB |
for UUT : wb_out_reg |
use entity work.wb_out_reg(wb_out_reg); |
end for; |
end for; |
end TB_wb_out_reg_16; |
/wb_vga/trunk/wb_tk/TestBench/wb_bus_dnsize_TB.vhd
0,0 → 1,174
--************************************************************* |
--* This file is automatically generated test bench template * |
--* By ACTIVE-VHDL <TBgen v1.10>. Copyright (C) ALDEC Inc. * |
--* * |
--* This file was generated on: 15:34, 2001.04.22. * |
--* Tested entity name: wb_bus_dnsize * |
--* File name contains tested entity: $DSN\src\wb_bus_dnsize.vhd * |
--************************************************************* |
|
library ieee,wb_tk,synopsys; |
use ieee.std_logic_1164.all; |
use wb_tk.technology.all; |
use synopsys.std_logic_arith.all; |
use wb_tk.wb_test.all; |
|
entity wb_bus_dnsize_tb is |
generic( |
m_bus_width : POSITIVE := 64; |
m_addr_width : POSITIVE := 6; |
s_bus_width : POSITIVE := 16; |
s_addr_width : POSITIVE := 8; |
little_endien : BOOLEAN := true ); |
end wb_bus_dnsize_tb; |
|
architecture TB of wb_bus_dnsize_tb is |
component wb_bus_dnsize |
generic( |
m_bus_width : POSITIVE := m_bus_width; |
m_addr_width : POSITIVE := m_addr_width; |
s_bus_width : POSITIVE := s_bus_width; |
s_addr_width : POSITIVE := s_addr_width; |
little_endien : BOOLEAN := little_endien |
); |
port( |
m_adr_i : in std_logic_vector((m_addr_width-1) downto 0); |
m_sel_i : in std_logic_vector(((m_bus_width/8)-1) downto 0); |
m_dat_i : in std_logic_vector((m_bus_width-1) downto 0); |
m_dat_oi : in std_logic_vector((m_bus_width-1) downto 0); |
m_dat_o : out std_logic_vector((m_bus_width-1) downto 0); |
m_cyc_i : in std_logic; |
m_ack_o : out std_logic; |
m_ack_oi : in std_logic; |
m_err_o : out std_logic; |
m_err_oi : in std_logic; |
m_rty_o : out std_logic; |
m_rty_oi : in std_logic; |
m_we_i : in std_logic; |
m_stb_i : in std_logic; |
s_adr_o : out std_logic_vector((s_addr_width-1) downto 0); |
s_sel_o : out std_logic_vector(((s_bus_width/8)-1) downto 0); |
s_dat_i : in std_logic_vector((s_bus_width-1) downto 0); |
s_dat_o : out std_logic_vector((s_bus_width-1) downto 0); |
s_cyc_o : out std_logic; |
s_ack_i : in std_logic; |
s_err_i : in std_logic; |
s_rty_i : in std_logic; |
s_we_o : out std_logic; |
s_stb_o : out std_logic |
); |
end component; |
|
-- Stimulus signals - signals mapped to the input and inout ports of tested entity |
signal m_adr_i : std_logic_vector((m_addr_width-1) downto 0); |
signal m_sel_i : std_logic_vector(((m_bus_width/8)-1) downto 0) := (others => '0'); |
signal m_dat_i : std_logic_vector((m_bus_width-1) downto 0); |
signal m_dat_oi : std_logic_vector((m_bus_width-1) downto 0) := (others => 'U'); |
signal m_cyc_i : std_logic; |
signal m_ack_oi : std_logic := 'U'; |
signal m_err_oi : std_logic := 'U'; |
signal m_rty_oi : std_logic := 'U'; |
signal m_we_i : std_logic; |
signal m_stb_i : std_logic; |
signal s_dat_i : std_logic_vector((s_bus_width-1) downto 0); |
signal s_ack_i : std_logic; |
signal s_err_i : std_logic; |
signal s_rty_i : std_logic; |
-- Observed signals - signals mapped to the output ports of tested entity |
signal m_dat_o : std_logic_vector((m_bus_width-1) downto 0); |
signal m_ack_o : std_logic; |
signal m_err_o : std_logic; |
signal m_rty_o : std_logic; |
signal s_adr_o : std_logic_vector((s_addr_width-1) downto 0); |
signal s_sel_o : std_logic_vector(((s_bus_width/8)-1) downto 0); |
signal s_dat_o : std_logic_vector((s_bus_width-1) downto 0); |
signal s_cyc_o : std_logic; |
signal s_we_o : std_logic; |
signal s_stb_o : std_logic; |
|
signal clk_i: std_logic; |
signal rst_i: std_logic; |
begin |
|
-- Unit Under Test port map |
UUT : wb_bus_dnsize |
port map |
(m_adr_i => m_adr_i, |
m_sel_i => m_sel_i, |
m_dat_i => m_dat_i, |
m_dat_oi => m_dat_oi, |
m_dat_o => m_dat_o, |
m_cyc_i => m_cyc_i, |
m_ack_o => m_ack_o, |
m_ack_oi => m_ack_oi, |
m_err_o => m_err_o, |
m_err_oi => m_err_oi, |
m_rty_o => m_rty_o, |
m_rty_oi => m_rty_oi, |
m_we_i => m_we_i, |
m_stb_i => m_stb_i, |
s_adr_o => s_adr_o, |
s_sel_o => s_sel_o, |
s_dat_i => s_dat_i, |
s_dat_o => s_dat_o, |
s_cyc_o => s_cyc_o, |
s_ack_i => s_ack_i, |
s_err_i => s_err_i, |
s_rty_i => s_rty_i, |
s_we_o => s_we_o, |
s_stb_o => s_stb_o ); |
|
clk: process is |
begin |
clk_i <= '0'; |
wait for 25ns; |
clk_i <= '1'; |
wait for 25ns; |
end process; |
|
reset: process is |
begin |
rst_i <= '1'; |
wait for 150ns; |
rst_i <= '0'; |
wait; |
end process; |
|
master: process is |
begin |
m_we_i <= '0'; |
m_cyc_i <= '0'; |
m_stb_i <= '0'; |
m_adr_i <= (others => '0'); |
m_dat_i <= (others => '0'); |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
|
wr_val(clk_i, m_adr_i,m_dat_o,m_dat_i,m_we_i,m_cyc_i,m_stb_i,m_ack_o,"000101","1111111011011100101110101001100001110110010101000011001000010000"); |
rd_val(clk_i, m_adr_i,m_dat_o,m_dat_i,m_we_i,m_cyc_i,m_stb_i,m_ack_o,"000101","1111111011011100101110101001100001110110010101000011001000010000"); |
-- wr_val(clk_i, m_adr_i,m_dat_o,m_dat_i,m_we_i,m_cyc_i,m_stb_i,m_ack_o,"000101","01110110010101000011001000010000"); |
-- rd_val(clk_i, m_adr_i,m_dat_o,m_dat_i,m_we_i,m_cyc_i,m_stb_i,m_ack_o,"000101","01110110010101000011001000010000"); |
|
m_sel_i <= add_one(m_sel_i); |
-- if (sel_i = "1111") then wait; end if; |
end process; |
|
s_ack_i <= s_stb_o; |
s_dat_i <= (others => '1'); |
s_err_i <= '0'; |
s_rty_i <= '0'; |
end TB; |
|
configuration TB_wb_bus_dnsize of wb_bus_dnsize_tb is |
for TB |
for UUT : wb_bus_dnsize |
use entity work.wb_bus_dnsize(wb_bus_dnsize); |
end for; |
end for; |
end TB_wb_bus_dnsize; |
|
/wb_vga/trunk/wb_tk/wb_async_slave.vhd
0,0 → 1,184
-- |
-- Wishbone bus toolkit. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
-- |
-- ELEMENTS: |
-- wb_async_slave: Wishbone bus to async (SRAM-like) bus slave bridge. |
|
------------------------------------------------------------------------------- |
-- |
-- wb_async_slave |
-- |
------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
|
entity wb_async_slave is |
generic ( |
width: positive := 16; |
addr_width: positive := 20 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- interface for wait-state generator state-machine |
wait_state: in std_logic_vector (3 downto 0); |
|
-- interface to wishbone master device |
adr_i: in std_logic_vector (addr_width-1 downto 0); |
sel_i: in std_logic_vector ((addr_width/8)-1 downto 0); |
dat_i: in std_logic_vector (width-1 downto 0); |
dat_o: out std_logic_vector (width-1 downto 0); |
dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-'); |
we_i: in std_logic; |
stb_i: in std_logic; |
ack_o: out std_logic := '0'; |
ack_oi: in std_logic := '-'; |
|
-- interface to async slave |
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z'); |
a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U'); |
a_rdn: out std_logic := '1'; |
a_wrn: out std_logic := '1'; |
a_cen: out std_logic := '1'; |
-- byte-enable signals |
a_byen: out std_logic_vector ((width/8)-1 downto 0) |
); |
end wb_async_slave; |
|
architecture wb_async_slave of wb_async_slave is |
-- multiplexed access signals to memory |
signal i_ack: std_logic; |
signal sm_ack: std_logic; |
|
type states is (sm_idle, sm_wait, sm_deact); |
signal state: states; |
signal cnt: std_logic_vector(3 downto 0); |
begin |
ack_o <= (stb_i and i_ack) or (not stb_i and ack_oi); |
dat_o_gen: for i in dat_o'RANGE generate |
dat_o(i) <= (stb_i and a_data(i)) or (not stb_i and dat_oi(i)); |
end generate; |
|
-- For 0WS operation i_ack is an async signal otherwise it's a sync one. |
i_ack_gen: process is |
begin |
wait on sm_ack, stb_i, wait_state, state; |
if (wait_state = "0000") then |
case (state) is |
when sm_deact => i_ack <= '0'; |
when others => i_ack <= stb_i; |
end case; |
else |
i_ack <= sm_ack; |
end if; |
end process; |
|
-- SRAM signal-handler process |
sram_signals: process is |
begin |
wait on state,we_i,a_data,adr_i,rst_i, stb_i, sel_i, dat_i; |
if (rst_i = '1') then |
a_wrn <= '1'; |
a_rdn <= '1'; |
a_cen <= '1'; |
a_addr <= (others => '-'); |
a_data <= (others => 'Z'); |
a_byen <= (others => '1'); |
else |
case (state) is |
when sm_deact => |
a_wrn <= '1'; |
a_rdn <= '1'; |
a_cen <= '1'; |
a_addr <= (others => '-'); |
a_data <= (others => 'Z'); |
a_byen <= (others => '1'); |
when others => |
a_addr <= adr_i; |
a_rdn <= not (not we_i and stb_i); |
a_wrn <= not (we_i and stb_i); |
a_cen <= not stb_i; |
a_byen <= not sel_i; |
if (we_i = '1') then |
a_data <= dat_i; |
else |
a_data <= (others => 'Z'); |
end if; |
end case; |
end if; |
end process; |
|
-- Aysnc access state-machine. |
async_sm: process is |
-- variable cnt: std_logic_vector(3 downto 0) := "0000"; |
-- variable state: states := init; |
begin |
wait until clk_i'EVENT and clk_i = '1'; |
if (rst_i = '1') then |
state <= sm_idle; |
cnt <= ((0) => '1', others => '0'); |
sm_ack <= '0'; |
else |
case (state) is |
when sm_idle => |
-- Check if anyone needs access to the memory. |
-- it's rdy signal will already be pulled low, so we only have to start the access |
if (stb_i = '1') then |
case wait_state is |
when "0000" => |
sm_ack <= '1'; |
state <= sm_deact; |
when "0001" => |
sm_ack <= '1'; |
cnt <= "0001"; |
state <= sm_wait; |
when others => |
sm_ack <= '0'; |
cnt <= "0001"; |
state <= sm_wait; |
end case; |
end if; |
when sm_wait => |
if (cnt = wait_state) then |
-- wait cycle completed. |
state <= sm_deact; |
sm_ack <= '0'; |
cnt <= "0000"; |
else |
if (add_one(cnt) = wait_state) then |
sm_ack <= '1'; |
else |
sm_ack <= '0'; |
end if; |
cnt <= add_one(cnt); |
end if; |
when sm_deact => |
if (stb_i = '1') then |
case wait_state is |
when "0000" => |
cnt <= "0000"; |
sm_ack <= '0'; |
state <= sm_wait; |
when others => |
sm_ack <= '0'; |
cnt <= "0000"; |
state <= sm_wait; |
end case; |
else |
sm_ack <= '0'; |
state <= sm_idle; |
end if; |
end case; |
end if; |
end process; |
end wb_async_slave; |
|
/wb_vga/trunk/wb_tk/gpl.txt
0,0 → 1,221
GNU GENERAL PUBLIC LICENSE |
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|
/wb_vga/trunk/wb_tk/wb_arbiter.vhd
0,0 → 1,245
-- |
-- Wishbone bus toolkit. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
-- |
-- ELEMENTS: |
-- wb_arbiter: two-way bus arbiter. Asyncronous logic ensures 0-ws operation on shared bus |
|
------------------------------------------------------------------------------- |
-- |
-- wb_arbiter |
-- |
------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
|
entity wb_arbiter is |
port ( |
-- clk: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- interface to master device a |
a_we_i: in std_logic; |
a_stb_i: in std_logic; |
a_cyc_i: in std_logic; |
a_ack_o: out std_logic; |
a_ack_oi: in std_logic := '-'; |
a_err_o: out std_logic; |
a_err_oi: in std_logic := '-'; |
a_rty_o: out std_logic; |
a_rty_oi: in std_logic := '-'; |
|
-- interface to master device b |
b_we_i: in std_logic; |
b_stb_i: in std_logic; |
b_cyc_i: in std_logic; |
b_ack_o: out std_logic; |
b_ack_oi: in std_logic := '-'; |
b_err_o: out std_logic; |
b_err_oi: in std_logic := '-'; |
b_rty_o: out std_logic; |
b_rty_oi: in std_logic := '-'; |
|
-- interface to shared devices |
s_we_o: out std_logic; |
s_stb_o: out std_logic; |
s_cyc_o: out std_logic; |
s_ack_i: in std_logic; |
s_err_i: in std_logic := '-'; |
s_rty_i: in std_logic := '-'; |
|
mux_signal: out std_logic; -- 0: select A signals, 1: select B signals |
|
-- misc control lines |
priority: in std_logic -- 0: A have priority over B, 1: B have priority over A |
); |
end wb_arbiter; |
|
-- This acthitecture is a clean asyncron state-machine. However it cannot be mapped to FPGA architecture |
architecture behaviour of wb_arbiter is |
type states is (idle,aa,ba); |
signal i_mux_signal: std_logic; |
|
signal e_state: states; |
begin |
mux_signal <= i_mux_signal; |
|
sm: process is |
variable state: states; |
begin |
wait on a_cyc_i, b_cyc_i, priority, rst_i; |
if (rst_i = '1') then |
state := idle; |
i_mux_signal <= priority; |
else |
case (state) is |
when idle => |
if (a_cyc_i = '1' and (priority = '0' or b_cyc_i = '0')) then |
state := aa; |
i_mux_signal <= '0'; |
elsif (b_cyc_i = '1' and (priority = '1' or a_cyc_i = '0')) then |
state := ba; |
i_mux_signal <= '1'; |
else |
i_mux_signal <= priority; |
end if; |
when aa => |
if (a_cyc_i = '0') then |
if (b_cyc_i = '1') then |
state := ba; |
i_mux_signal <= '1'; |
else |
state := idle; |
i_mux_signal <= priority; |
end if; |
else |
i_mux_signal <= '0'; |
end if; |
when ba => |
if (b_cyc_i = '0') then |
if (a_cyc_i = '1') then |
state := aa; |
i_mux_signal <= '0'; |
else |
state := idle; |
i_mux_signal <= priority; |
end if; |
else |
i_mux_signal <= '1'; |
end if; |
end case; |
end if; |
e_state <= state; |
end process; |
|
signal_mux: process is |
begin |
wait on a_we_i, a_stb_i, a_ack_oi, a_err_oi, a_rty_oi, a_cyc_i, |
b_we_i, b_stb_i, b_ack_oi, b_err_oi, b_rty_oi, b_cyc_i, |
s_ack_i, s_err_i, s_rty_i, i_mux_signal; |
if (i_mux_signal = '0') then |
s_we_o <= a_we_i; |
s_stb_o <= a_stb_i; |
s_cyc_o <= a_cyc_i; |
a_ack_o <= (a_stb_i and s_ack_i) or (not a_stb_i and a_ack_oi); |
a_err_o <= (a_stb_i and s_err_i) or (not a_stb_i and a_err_oi); |
a_rty_o <= (a_stb_i and s_rty_i) or (not a_stb_i and a_rty_oi); |
b_ack_o <= (b_stb_i and '0') or (not b_stb_i and b_ack_oi); |
b_err_o <= (b_stb_i and '0') or (not b_stb_i and b_err_oi); |
b_rty_o <= (b_stb_i and '0') or (not b_stb_i and b_rty_oi); |
else |
s_we_o <= b_we_i; |
s_stb_o <= b_stb_i; |
s_cyc_o <= b_cyc_i; |
b_ack_o <= (b_stb_i and s_ack_i) or (not b_stb_i and b_ack_oi); |
b_err_o <= (b_stb_i and s_err_i) or (not b_stb_i and b_err_oi); |
b_rty_o <= (b_stb_i and s_rty_i) or (not b_stb_i and b_rty_oi); |
a_ack_o <= (a_stb_i and '0') or (not a_stb_i and a_ack_oi); |
a_err_o <= (a_stb_i and '0') or (not a_stb_i and a_err_oi); |
a_rty_o <= (a_stb_i and '0') or (not a_stb_i and a_rty_oi); |
end if; |
end process; |
end behaviour; |
|
-- This acthitecture is a more-or-less structural implementation. Fits for FPGA realization. |
architecture FPGA of wb_arbiter is |
component d_ff |
port ( d : in STD_LOGIC; |
clk: in STD_LOGIC; |
ena: in STD_LOGIC := '1'; |
clr: in STD_LOGIC := '0'; |
pre: in STD_LOGIC := '0'; |
q : out STD_LOGIC |
); |
end component; |
|
signal i_mux_signal: std_logic; |
|
type states is (idle,aa,ba,XX); |
signal e_state: states; |
|
-- signals for a DFF in FPGA |
signal idle_s, aa_s, ba_s: std_logic; |
|
signal aa_clk, aa_ena, aa_clr, aa_pre: std_logic; |
signal ba_clk, ba_ena, ba_clr, ba_pre: std_logic; |
|
begin |
mux_signal <= i_mux_signal; |
|
idle_s <= not (a_cyc_i or b_cyc_i); |
|
aa_clr <= rst_i or not a_cyc_i; |
aa_clk <= a_cyc_i; |
aa_ena <= not b_cyc_i and priority; |
aa_pre <= (a_cyc_i and not priority and not ba_s) or (a_cyc_i and not b_cyc_i); |
aa_ff: d_ff port map ( |
d => '1', |
clk => aa_clk, |
ena => aa_ena, |
clr => aa_clr, |
pre => aa_pre, |
q => aa_s |
); |
|
ba_clr <= rst_i or not b_cyc_i; |
ba_clk <= b_cyc_i; |
ba_ena <= not a_cyc_i and not priority; |
ba_pre <= (b_cyc_i and priority and not aa_s) or (b_cyc_i and not a_cyc_i); |
ba_ff: d_ff port map ( |
d => '1', |
clk => ba_clk, |
ena => ba_ena, |
clr => ba_clr, |
pre => ba_pre, |
q => ba_s |
); |
|
i_mux_signal <= (priority and idle_s) or ba_s; |
|
signal_mux: process is |
begin |
wait on a_we_i, a_stb_i, a_ack_oi, a_err_oi, a_rty_oi, a_cyc_i, |
b_we_i, b_stb_i, b_ack_oi, b_err_oi, b_rty_oi, b_cyc_i, |
s_ack_i, s_err_i, s_rty_i, i_mux_signal; |
if (i_mux_signal = '0') then |
s_we_o <= a_we_i; |
s_stb_o <= a_stb_i; |
s_cyc_o <= a_cyc_i; |
a_ack_o <= (a_stb_i and s_ack_i) or (not a_stb_i and a_ack_oi); |
a_err_o <= (a_stb_i and s_err_i) or (not a_stb_i and a_err_oi); |
a_rty_o <= (a_stb_i and s_rty_i) or (not a_stb_i and a_rty_oi); |
b_ack_o <= (b_stb_i and '0') or (not b_stb_i and b_ack_oi); |
b_err_o <= (b_stb_i and '0') or (not b_stb_i and b_err_oi); |
b_rty_o <= (b_stb_i and '0') or (not b_stb_i and b_rty_oi); |
else |
s_we_o <= b_we_i; |
s_stb_o <= b_stb_i; |
s_cyc_o <= b_cyc_i; |
b_ack_o <= (b_stb_i and s_ack_i) or (not b_stb_i and b_ack_oi); |
b_err_o <= (b_stb_i and s_err_i) or (not b_stb_i and b_err_oi); |
b_rty_o <= (b_stb_i and s_rty_i) or (not b_stb_i and b_rty_oi); |
a_ack_o <= (a_stb_i and '0') or (not a_stb_i and a_ack_oi); |
a_err_o <= (a_stb_i and '0') or (not a_stb_i and a_err_oi); |
a_rty_o <= (a_stb_i and '0') or (not a_stb_i and a_rty_oi); |
end if; |
end process; |
|
gen_e_state: process is |
begin |
wait on idle_s,aa_s,ba_s; |
if (idle_s = '1' and ba_s = '0' and aa_s = '0') then e_state <= idle; |
elsif (idle_s = '0' and ba_s = '1' and aa_s = '0') then e_state <= aa; |
elsif (idle_s = '0' and ba_s = '0' and aa_s = '1') then e_state <= ba; |
else e_state <= XX; |
end if; |
end process; |
end FPGA; |
|
/wb_vga/trunk/wb_tk/wb_async_master.vhd
0,0 → 1,127
-- |
-- Wishbone bus toolkit. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
-- |
-- ELEMENTS: |
-- wb_async_master: async bus master to Wishbone bus bridge. |
|
------------------------------------------------------------------------------- |
-- |
-- wb_async_master |
-- |
------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
|
entity wb_async_master is |
generic ( |
width: positive := 16; |
addr_width: positive := 20 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- interface to wb slave devices |
s_adr_o: out std_logic_vector (addr_width-1 downto 0); |
s_sel_o: out std_logic_vector ((width/8)-1 downto 0); |
s_dat_i: in std_logic_vector (width-1 downto 0); |
s_dat_o: out std_logic_vector (width-1 downto 0); |
s_cyc_o: out std_logic; |
s_ack_i: in std_logic; |
s_err_i: in std_logic := '-'; |
s_rty_i: in std_logic := '-'; |
s_we_o: out std_logic; |
s_stb_o: out std_logic; |
|
-- interface to asyncron master device |
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z'); |
a_addr: in std_logic_vector (addr_width-1 downto 0) := (others => 'U'); |
a_rdn: in std_logic := '1'; |
a_wrn: in std_logic := '1'; |
a_cen: in std_logic := '1'; |
a_byen: in std_logic_vector ((width/8)-1 downto 0); |
a_waitn: out std_logic |
); |
end wb_async_master; |
|
architecture wb_async_master of wb_async_master is |
component d_ff |
port ( d : in STD_LOGIC; |
clk: in STD_LOGIC; |
ena: in STD_LOGIC := '1'; |
clr: in STD_LOGIC := '0'; |
pre: in STD_LOGIC := '0'; |
q : out STD_LOGIC |
); |
end component; |
signal wg_clk, wg_pre, wg_q: std_logic; |
signal i_cyc_o, i_stb_o, i_we_o: std_logic; |
signal i_waitn: std_logic; |
begin |
ctrl: process is |
begin |
wait until clk_i'EVENT and clk_i = '1'; |
if (rst_i = '1') then |
i_cyc_o <= '0'; |
i_stb_o <= '0'; |
i_we_o <= '0'; |
else |
if (a_cen = '0') then |
i_stb_o <= not (a_rdn and a_wrn); |
i_we_o <= not a_wrn; |
i_cyc_o <= '1'; |
else |
i_cyc_o <= '0'; |
i_stb_o <= '0'; |
i_we_o <= '0'; |
end if; |
end if; |
end process; |
s_cyc_o <= i_cyc_o and not i_waitn; |
s_stb_o <= i_stb_o and not i_waitn; |
s_we_o <= i_we_o and not i_waitn; |
|
w_ff1: d_ff port map ( |
d => s_ack_i, |
clk => clk_i, |
ena => '1', |
clr => rst_i, |
pre => '0', |
q => wg_q |
); |
|
wg_clk <= not a_cen; |
wg_pre <= wg_q or rst_i; |
w_ff2: d_ff port map ( |
d => '0', |
clk => wg_clk, |
ena => '1', |
clr => '0', |
pre => wg_pre, |
q => i_waitn |
); |
a_waitn <= i_waitn; |
|
s_adr_o <= a_addr; |
negate: for i in s_sel_o'RANGE generate s_sel_o(i) <= not a_byen(i); end generate; |
s_dat_o <= a_data; |
|
a_data_out: process is |
begin |
wait on s_dat_i, a_rdn, a_cen; |
if (a_rdn = '0' and a_cen = '0') then |
a_data <= s_dat_i; |
else |
a_data <= (others => 'Z'); |
end if; |
end process; |
end wb_async_master; |
|
/wb_vga/trunk/wb_tk/wb_bus_upsize.vhd
0,0 → 1,111
-- |
-- Wishbone bus toolkit. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
-- |
-- ELEMENTS: |
-- wb_bus_upsize: bus upsizer. |
|
------------------------------------------------------------------------------- |
-- |
-- wb_bus_upsize |
-- |
------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
|
entity wb_bus_upsize is |
generic ( |
m_bus_width: positive := 8; -- master bus width |
m_addr_width: positive := 21; -- master bus width |
s_bus_width: positive := 16; -- slave bus width |
s_addr_width: positive := 20; -- master bus width |
little_endien: boolean := true -- if set to false, big endien |
); |
port ( |
-- clk_i: in std_logic; |
-- rst_i: in std_logic := '0'; |
|
-- Master bus interface |
m_adr_i: in std_logic_vector (m_addr_width-1 downto 0); |
m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1'); |
m_dat_i: in std_logic_vector (m_bus_width-1 downto 0); |
m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-'); |
m_dat_o: out std_logic_vector (m_bus_width-1 downto 0); |
m_cyc_i: in std_logic; |
m_ack_o: out std_logic; |
m_ack_oi: in std_logic := '-'; |
m_err_o: out std_logic; |
m_err_oi: in std_logic := '-'; |
m_rty_o: out std_logic; |
m_rty_oi: in std_logic := '-'; |
m_we_i: in std_logic; |
m_stb_i: in std_logic; |
|
-- Slave bus interface |
s_adr_o: out std_logic_vector (s_addr_width-1 downto 0); |
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0); |
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0); |
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0); |
s_cyc_o: out std_logic; |
s_ack_i: in std_logic; |
s_err_i: in std_logic := '-'; |
s_rty_i: in std_logic := '-'; |
s_we_o: out std_logic; |
s_stb_o: out std_logic |
); |
end wb_bus_upsize; |
|
architecture wb_bus_upsize of wb_bus_upsize is |
constant addr_diff: integer := log2(s_bus_width/m_bus_width); |
signal i_m_dat_o: std_logic_vector(m_bus_width-1 downto 0); |
begin |
assert (m_addr_width = s_addr_width+addr_diff) report "Address widths are not consistent" severity FAILURE; |
s_adr_o <= m_adr_i(m_addr_width-addr_diff downto addr_diff); |
s_we_o <= m_we_i; |
m_ack_o <= (m_stb_i and s_ack_i) or (not m_stb_i and m_ack_oi); |
m_err_o <= (m_stb_i and s_err_i) or (not m_stb_i and m_err_oi); |
m_rty_o <= (m_stb_i and s_rty_i) or (not m_stb_i and m_rty_oi); |
s_stb_o <= m_stb_i; |
s_cyc_o <= m_cyc_i; |
|
|
sel_dat_mux: process is |
begin |
wait on s_dat_i, m_adr_i; |
if (little_endien) then |
for i in s_sel_o'RANGE loop |
if (equ(m_adr_i(addr_diff-1 downto 0),i)) then |
s_sel_o(i) <= '1'; |
i_m_dat_o <= s_dat_i(8*i+7 downto 8*i+0); |
else |
s_sel_o(i) <= '0'; |
end if; |
end loop; |
else |
for i in s_sel_o'RANGE loop |
if (equ(m_adr_i(addr_diff-1 downto 0),i)) then |
s_sel_o(s_sel_o'HIGH-i) <= '1'; |
i_m_dat_o <= s_dat_i(s_dat_i'HIGH-8*i downto s_dat_i'HIGH-8*i-7); |
else |
s_sel_o(s_sel_o'HIGH-i) <= '0'; |
end if; |
end loop; |
end if; |
end process; |
|
d_i_for: for i in m_dat_o'RANGE generate |
m_dat_o(i) <= (m_stb_i and i_m_dat_o(i)) or (not m_stb_i and m_dat_oi(i)); |
end generate; |
|
d_o_for: for i in s_sel_o'RANGE generate |
s_dat_o(8*i+7 downto 8*i+0) <= m_dat_i; |
end generate; |
end wb_bus_upsize; |
|
/wb_vga/trunk/wb_tk/compile.sh
0,0 → 1,78
#!/bin/bash |
# |
# Script to compile sources to a library using Active HDL |
# (c) Copyright Andras Tantos <tantos@opencores.org> 2001/04/25 |
# This code is distributed under the terms and conditions of the GNU General Public Lince. |
# |
# USAGE: |
# |
# Set APATH to the installation directory of ActiveHDL and |
# LIB to whatever name your library has |
# RESULT_PATH to where generated files you wish to be put |
# Also make sure that you upadted the Library.cfg file to contain |
# the specified library name. |
# After the common part, list all files you wish to include in your library |
# with 'compile_file' preciding the file name. |
# |
# NOTES: |
# |
# This script depends on the following executables: |
# bash |
# cat |
# rm |
# mv |
# mkdir |
# echo |
# test |
# they are available under all UNIX-es and can be installed for windows |
# and DOS too. The windows version of these files can be obtained from |
# GNU Cygnus distribution (http://sources.redhat.com/cygwin) |
# The minimal package of these utilities are also available from |
# OpenCores web-site. |
|
APATH=C:/CAED/ActiveHDL.36/ |
LIB=wb_tk |
RESULT_PATH=ahdl |
|
# ___________Common part of the script____________ |
|
LIB_FILE=$RESULT_PATH/$LIB.lib |
CMP_FILE=$RESULT_PATH/0.mgf |
CMP=$APATH/bin/acombat.exe |
CMP_FLAGS="-avhdl $APATH -lib $LIB -93" |
|
compile_file() { |
LOG_FILE=$1 |
LOG_FILE=$RESULT_PATH/${LOG_FILE/.vhd/.rlt} |
ERR_FILE=${LOG_FILE/.rtl/.err} |
rm -f $LOG_FILE |
rm -f $ERR_FILE |
$CMP $CMP_FLAGS -log $LOG_FILE $1 || { |
mv $LOG_FILE $ERR_FILE |
cat $ERR_FILE |
exit 1 |
} |
cat $LOG_FILE |
} |
|
if test ! -d $RESULT_PATH; then |
mkdir $RESULT_PATH |
fi |
rm -f $RESULT_PATH/* |
if test ! -f $LIB_FILE; then |
echo > $LIB_FILE |
fi |
# ___________End of common part of the script____________ |
|
compile_file technology.vhd |
compile_file wb_arbiter.vhd |
compile_file wb_async_master.vhd |
compile_file wb_async_slave.vhd |
compile_file wb_bus_dnsize.vhd |
compile_file wb_bus_upsize.vhd |
compile_file wb_bus_resize.vhd |
compile_file wb_out_reg.vhd |
compile_file wb_ram.vhd |
compile_file wb_test.vhd |
compile_file wb_tk.vhd |
|
/wb_vga/trunk/wb_tk/wb_bus_resize.vhd
0,0 → 1,249
-- |
-- Wishbone bus toolkit. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
-- |
-- ELEMENTS: |
-- wb_bus_resize: bus resizer. |
|
------------------------------------------------------------------------------- |
-- |
-- wb_bus_resize |
-- |
------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
use wb_tk.all; |
|
entity wb_bus_resize is |
generic ( |
m_bus_width: positive := 32; -- master bus width |
m_addr_width: positive := 19; -- master bus width |
s_bus_width: positive := 16; -- slave bus width |
s_addr_width: positive := 20; -- master bus width |
little_endien: boolean := true -- if set to false, big endien |
); |
port ( |
-- clk_i: in std_logic; |
-- rst_i: in std_logic := '0'; |
|
-- Master bus interface |
m_adr_i: in std_logic_vector (m_addr_width-1 downto 0); |
m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1'); |
m_dat_i: in std_logic_vector (m_bus_width-1 downto 0); |
m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-'); |
m_dat_o: out std_logic_vector (m_bus_width-1 downto 0); |
m_cyc_i: in std_logic; |
m_ack_o: out std_logic; |
m_ack_oi: in std_logic := '-'; |
m_err_o: out std_logic; |
m_err_oi: in std_logic := '-'; |
m_rty_o: out std_logic; |
m_rty_oi: in std_logic := '-'; |
m_we_i: in std_logic; |
m_stb_i: in std_logic; |
|
-- Slave bus interface |
s_adr_o: out std_logic_vector (s_addr_width-1 downto 0); |
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0); |
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0); |
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0); |
s_cyc_o: out std_logic; |
s_ack_i: in std_logic; |
s_err_i: in std_logic := '-'; |
s_rty_i: in std_logic := '-'; |
s_we_o: out std_logic; |
s_stb_o: out std_logic |
); |
end wb_bus_resize; |
|
architecture wb_bus_resize of wb_bus_resize is |
component wb_bus_upsize is |
generic ( |
m_bus_width: positive := 8; -- master bus width |
m_addr_width: positive := 21; -- master bus width |
s_bus_width: positive := 16; -- slave bus width |
s_addr_width: positive := 20; -- master bus width |
little_endien: boolean := true -- if set to false, big endien |
); |
port ( |
-- clk_i: in std_logic; |
-- rst_i: in std_logic := '0'; |
|
-- Master bus interface |
m_adr_i: in std_logic_vector (m_addr_width-1 downto 0); |
m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1'); |
m_dat_i: in std_logic_vector (m_bus_width-1 downto 0); |
m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-'); |
m_dat_o: out std_logic_vector (m_bus_width-1 downto 0); |
m_cyc_i: in std_logic; |
m_ack_o: out std_logic; |
m_ack_oi: in std_logic := '-'; |
m_err_o: out std_logic; |
m_err_oi: in std_logic := '-'; |
m_rty_o: out std_logic; |
m_rty_oi: in std_logic := '-'; |
m_we_i: in std_logic; |
m_stb_i: in std_logic; |
|
-- Slave bus interface |
s_adr_o: out std_logic_vector (s_addr_width-1 downto 0); |
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0); |
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0); |
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0); |
s_cyc_o: out std_logic; |
s_ack_i: in std_logic; |
s_err_i: in std_logic := '-'; |
s_rty_i: in std_logic := '-'; |
s_we_o: out std_logic; |
s_stb_o: out std_logic |
); |
end component; |
|
component wb_bus_dnsize is |
generic ( |
m_bus_width: positive := 32; -- master bus width |
m_addr_width: positive := 20; -- master bus width |
s_bus_width: positive := 16; -- slave bus width |
s_addr_width: positive := 21; -- master bus width |
little_endien: boolean := true -- if set to false, big endien |
); |
port ( |
-- clk_i: in std_logic; |
-- rst_i: in std_logic := '0'; |
|
-- Master bus interface |
m_adr_i: in std_logic_vector (m_addr_width-1 downto 0); |
m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1'); |
m_dat_i: in std_logic_vector (m_bus_width-1 downto 0); |
m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-'); |
m_dat_o: out std_logic_vector (m_bus_width-1 downto 0); |
m_cyc_i: in std_logic; |
m_ack_o: out std_logic; |
m_ack_oi: in std_logic := '-'; |
m_err_o: out std_logic; |
m_err_oi: in std_logic := '-'; |
m_rty_o: out std_logic; |
m_rty_oi: in std_logic := '-'; |
m_we_i: in std_logic; |
m_stb_i: in std_logic; |
|
-- Slave bus interface |
s_adr_o: out std_logic_vector (s_addr_width-1 downto 0); |
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0); |
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0); |
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0); |
s_cyc_o: out std_logic; |
s_ack_i: in std_logic; |
s_err_i: in std_logic := '-'; |
s_rty_i: in std_logic := '-'; |
s_we_o: out std_logic; |
s_stb_o: out std_logic |
); |
end component; |
begin |
dn_sel: if (m_bus_width > s_bus_width) generate |
dnsizer: wb_bus_dnsize |
generic map ( |
m_bus_width => m_bus_width, |
m_addr_width => m_addr_width, |
s_bus_width => s_bus_width, |
s_addr_width => s_addr_width, |
little_endien => little_endien |
) |
port map |
(m_adr_i => m_adr_i, |
m_sel_i => m_sel_i, |
m_dat_i => m_dat_i, |
m_dat_oi => m_dat_oi, |
m_dat_o => m_dat_o, |
m_cyc_i => m_cyc_i, |
m_ack_o => m_ack_o, |
m_ack_oi => m_ack_oi, |
m_err_o => m_err_o, |
m_err_oi => m_err_oi, |
m_rty_o => m_rty_o, |
m_rty_oi => m_rty_oi, |
m_we_i => m_we_i, |
m_stb_i => m_stb_i, |
s_adr_o => s_adr_o, |
s_sel_o => s_sel_o, |
s_dat_i => s_dat_i, |
s_dat_o => s_dat_o, |
s_cyc_o => s_cyc_o, |
s_ack_i => s_ack_i, |
s_err_i => s_err_i, |
s_rty_i => s_rty_i, |
s_we_o => s_we_o, |
s_stb_o => s_stb_o |
); |
end generate; |
up_sel: if (m_bus_width < s_bus_width) generate |
upsizer: wb_bus_upsize |
generic map ( |
m_bus_width => m_bus_width, |
m_addr_width => m_addr_width, |
s_bus_width => s_bus_width, |
s_addr_width => s_addr_width, |
little_endien => little_endien |
) |
port map |
(m_adr_i => m_adr_i, |
m_sel_i => m_sel_i, |
m_dat_i => m_dat_i, |
m_dat_oi => m_dat_oi, |
m_dat_o => m_dat_o, |
m_cyc_i => m_cyc_i, |
m_ack_o => m_ack_o, |
m_ack_oi => m_ack_oi, |
m_err_o => m_err_o, |
m_err_oi => m_err_oi, |
m_rty_o => m_rty_o, |
m_rty_oi => m_rty_oi, |
m_we_i => m_we_i, |
m_stb_i => m_stb_i, |
s_adr_o => s_adr_o, |
s_sel_o => s_sel_o, |
s_dat_i => s_dat_i, |
s_dat_o => s_dat_o, |
s_cyc_o => s_cyc_o, |
s_ack_i => s_ack_i, |
s_err_i => s_err_i, |
s_rty_i => s_rty_i, |
s_we_o => s_we_o, |
s_stb_o => s_stb_o |
); |
end generate; |
eq_sel: if (m_bus_width = s_bus_width) generate |
dat_o_for: for i in m_dat_o'RANGE generate |
dat_o_gen: m_dat_o(i) <= (s_dat_i(i) and m_stb_i and not m_we_i) or (m_dat_oi(i) and not (m_stb_i and not m_we_i)); |
end generate; |
m_ack_o <= (s_ack_i and m_stb_i and not m_we_i) or (m_ack_oi and not (m_stb_i and not m_we_i)); |
m_err_o <= (s_err_i and m_stb_i and not m_we_i) or (m_err_oi and not (m_stb_i and not m_we_i)); |
m_rty_o <= (s_rty_i and m_stb_i and not m_we_i) or (m_rty_oi and not (m_stb_i and not m_we_i)); |
s_adr_o <= m_adr_i; |
s_sel_o <= m_sel_i; |
s_dat_o <= m_dat_i; |
s_cyc_o <= m_cyc_i; |
s_we_o <= m_we_i; |
s_stb_o <= m_stb_i; |
end generate; |
end wb_bus_resize; |
|
--configuration c_wb_bus_resize of wb_bus_resize is |
-- for wb_bus_resize |
-- for dnsizer: wb_bus_dnsize |
-- use entity wb_bus_dnsize(wb_bus_dnsize); |
-- end for; |
-- for upsizer: wb_bus_upsize |
-- use entity wb_bus_upsize(wb_bus_upsize); |
-- end for; |
-- end for; |
--end c_wb_bus_resize; |
|
/wb_vga/trunk/wb_tk/wb_tk.vhd
0,0 → 1,280
-- |
-- Wishbone bus toolkit. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
-- |
-- ELEMENTS: |
-- wb_bus_upsize: bus upsizer. Currently only 8->16 bit bus resize is supported |
-- wb_async_slave: Wishbone bus to async (SRAM-like) bus slave bridge. |
-- wb_arbiter: two-way bus arbiter. Asyncronous logic ensures 0-ws operation on shared bus |
-- wb_out_reg: Wishbone bus compatible output register. |
-- wb_bus_resize: Wishbone bus resizer. |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
library wb_tk; |
use wb_tk.technology.all; |
|
package wb_tk is |
component wb_bus_upsize is |
generic ( |
m_bus_width: positive := 8; -- master bus width |
m_addr_width: positive := 21; -- master bus width |
s_bus_width: positive := 16; -- slave bus width |
s_addr_width: positive := 20; -- master bus width |
little_endien: boolean := true -- if set to false, big endien |
); |
port ( |
-- clk_i: in std_logic; |
-- rst_i: in std_logic := '0'; |
|
-- Master bus interface |
m_adr_i: in std_logic_vector (m_addr_width-1 downto 0); |
m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1'); |
m_dat_i: in std_logic_vector (m_bus_width-1 downto 0); |
m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-'); |
m_dat_o: out std_logic_vector (m_bus_width-1 downto 0); |
m_cyc_i: in std_logic; |
m_ack_o: out std_logic; |
m_ack_oi: in std_logic := '-'; |
m_err_o: out std_logic; |
m_err_oi: in std_logic := '-'; |
m_rty_o: out std_logic; |
m_rty_oi: in std_logic := '-'; |
m_we_i: in std_logic; |
m_stb_i: in std_logic; |
|
-- Slave bus interface |
s_adr_o: out std_logic_vector (s_addr_width-1 downto 0); |
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0); |
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0); |
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0); |
s_cyc_o: out std_logic; |
s_ack_i: in std_logic; |
s_err_i: in std_logic := '-'; |
s_rty_i: in std_logic := '-'; |
s_we_o: out std_logic; |
s_stb_o: out std_logic |
); |
end component; |
|
component wb_bus_dnsize is |
generic ( |
m_bus_width: positive := 32; -- master bus width |
m_addr_width: positive := 20; -- master bus width |
s_bus_width: positive := 16; -- slave bus width |
s_addr_width: positive := 21; -- master bus width |
little_endien: boolean := true -- if set to false, big endien |
); |
port ( |
-- clk_i: in std_logic; |
-- rst_i: in std_logic := '0'; |
|
-- Master bus interface |
m_adr_i: in std_logic_vector (m_addr_width-1 downto 0); |
m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1'); |
m_dat_i: in std_logic_vector (m_bus_width-1 downto 0); |
m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-'); |
m_dat_o: out std_logic_vector (m_bus_width-1 downto 0); |
m_cyc_i: in std_logic; |
m_ack_o: out std_logic; |
m_ack_oi: in std_logic := '-'; |
m_err_o: out std_logic; |
m_err_oi: in std_logic := '-'; |
m_rty_o: out std_logic; |
m_rty_oi: in std_logic := '-'; |
m_we_i: in std_logic; |
m_stb_i: in std_logic; |
|
-- Slave bus interface |
s_adr_o: out std_logic_vector (s_addr_width-1 downto 0); |
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0); |
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0); |
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0); |
s_cyc_o: out std_logic; |
s_ack_i: in std_logic; |
s_err_i: in std_logic := '-'; |
s_rty_i: in std_logic := '-'; |
s_we_o: out std_logic; |
s_stb_o: out std_logic |
); |
end component; |
|
component wb_bus_resize is |
generic ( |
m_bus_width: positive := 32; -- master bus width |
m_addr_width: positive := 20; -- master bus width |
s_bus_width: positive := 16; -- slave bus width |
s_addr_width: positive := 21; -- master bus width |
little_endien: boolean := true -- if set to false, big endien |
); |
port ( |
-- clk_i: in std_logic; |
-- rst_i: in std_logic := '0'; |
|
-- Master bus interface |
m_adr_i: in std_logic_vector (m_addr_width-1 downto 0); |
m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1'); |
m_dat_i: in std_logic_vector (m_bus_width-1 downto 0); |
m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-'); |
m_dat_o: out std_logic_vector (m_bus_width-1 downto 0); |
m_cyc_i: in std_logic; |
m_ack_o: out std_logic; |
m_ack_oi: in std_logic := '-'; |
m_err_o: out std_logic; |
m_err_oi: in std_logic := '-'; |
m_rty_o: out std_logic; |
m_rty_oi: in std_logic := '-'; |
m_we_i: in std_logic; |
m_stb_i: in std_logic; |
|
-- Slave bus interface |
s_adr_o: out std_logic_vector (s_addr_width-1 downto 0); |
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0); |
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0); |
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0); |
s_cyc_o: out std_logic; |
s_ack_i: in std_logic; |
s_err_i: in std_logic := '-'; |
s_rty_i: in std_logic := '-'; |
s_we_o: out std_logic; |
s_stb_o: out std_logic |
); |
end component; |
|
component wb_async_master is |
generic ( |
width: positive := 16; |
addr_width: positive := 20 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- interface to wb slave devices |
s_adr_o: out std_logic_vector (addr_width-1 downto 0); |
s_sel_o: out std_logic_vector ((width/8)-1 downto 0); |
s_dat_i: in std_logic_vector (width-1 downto 0); |
s_dat_o: out std_logic_vector (width-1 downto 0); |
s_cyc_o: out std_logic; |
s_ack_i: in std_logic; |
s_err_i: in std_logic := '-'; |
s_rty_i: in std_logic := '-'; |
s_we_o: out std_logic; |
s_stb_o: out std_logic; |
|
-- interface to asyncron master device |
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z'); |
a_addr: in std_logic_vector (addr_width-1 downto 0) := (others => 'U'); |
a_rdn: in std_logic := '1'; |
a_wrn: in std_logic := '1'; |
a_cen: in std_logic := '1'; |
a_byen: in std_logic_vector ((width/8)-1 downto 0); |
a_waitn: out std_logic |
); |
end component; |
|
component wb_async_slave is |
generic ( |
width: positive := 16; |
addr_width: positive := 20 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- interface for wait-state generator state-machine |
wait_state: in std_logic_vector (3 downto 0); |
|
-- interface to wishbone master device |
adr_i: in std_logic_vector (addr_width-1 downto 0); |
sel_i: in std_logic_vector ((addr_width/8)-1 downto 0); |
dat_i: in std_logic_vector (width-1 downto 0); |
dat_o: out std_logic_vector (width-1 downto 0); |
dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-'); |
we_i: in std_logic; |
stb_i: in std_logic; |
ack_o: out std_logic := '0'; |
ack_oi: in std_logic := '-'; |
|
-- interface to async slave |
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z'); |
a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U'); |
a_rdn: out std_logic := '1'; |
a_wrn: out std_logic := '1'; |
a_cen: out std_logic := '1'; |
-- byte-enable signals |
a_byen: out std_logic_vector ((width/8)-1 downto 0) |
); |
end component; |
|
component wb_arbiter is |
port ( |
-- clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- interface to master device a |
a_we_i: in std_logic; |
a_stb_i: in std_logic; |
a_cyc_i: in std_logic; |
a_ack_o: out std_logic; |
a_ack_oi: in std_logic := '-'; |
a_err_o: out std_logic; |
a_err_oi: in std_logic := '-'; |
a_rty_o: out std_logic; |
a_rty_oi: in std_logic := '-'; |
|
-- interface to master device b |
b_we_i: in std_logic; |
b_stb_i: in std_logic; |
b_cyc_i: in std_logic; |
b_ack_o: out std_logic; |
b_ack_oi: in std_logic := '-'; |
b_err_o: out std_logic; |
b_err_oi: in std_logic := '-'; |
b_rty_o: out std_logic; |
b_rty_oi: in std_logic := '-'; |
|
-- interface to shared devices |
s_we_o: out std_logic; |
s_stb_o: out std_logic; |
s_cyc_o: out std_logic; |
s_ack_i: in std_logic; |
s_err_i: in std_logic := '-'; |
s_rty_i: in std_logic := '-'; |
|
mux_signal: out std_logic; -- 0: select A signals, 1: select B signals |
|
-- misc control lines |
priority: in std_logic -- 0: A have priority over B, 1: B have priority over A |
); |
end component; |
|
component wb_out_reg is |
generic ( |
width : positive := 8; |
bus_width: positive := 8; |
offset: integer := 0 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic; |
rst_val: std_logic_vector(width-1 downto 0) := (others => '0'); |
|
cyc_i: in std_logic := '1'; |
stb_i: in std_logic; |
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1'); |
we_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0'); |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
q: out std_logic_vector (width-1 downto 0) |
); |
end component; |
end wb_tk; |
|
/wb_vga/trunk/wb_tk/wb_ram.vhd
0,0 → 1,85
-- |
-- Wishbone bus toolkit. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
-- |
-- ELEMENTS: |
-- wb_ram: ram element. |
|
------------------------------------------------------------------------------- |
-- |
-- wb_ram |
-- |
------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
|
entity wb_ram is |
generic ( |
data_width: positive := 8; |
addr_width: positive := 10 |
); |
port ( |
clk_i: in std_logic; |
-- rst_i: in std_logic := '0'; |
adr_i: in std_logic_vector (addr_width-1 downto 0); |
-- sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1'); |
dat_i: in std_logic_vector (data_width-1 downto 0); |
dat_oi: in std_logic_vector (data_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (data_width-1 downto 0); |
cyc_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
-- err_o: out std_logic; |
-- err_oi: in std_logic := '-'; |
-- rty_o: out std_logic; |
-- rty_oi: in std_logic := '-'; |
we_i: in std_logic; |
stb_i: in std_logic |
); |
end wb_ram; |
|
architecture wb_ram of wb_ram is |
component ram |
generic ( |
data_width : positive; |
addr_width : positive |
); |
port ( |
clk : in std_logic; |
we : in std_logic; |
addr : in std_logic_vector(addr_width-1 downto 0); |
d_in : in std_logic_vector(data_width-1 downto 0); |
d_out : out std_logic_vector(data_width-1 downto 0) |
); |
end component; |
|
signal mem_we: std_logic; |
signal mem_dat_o: std_logic_vector(data_width-1 downto 0); |
begin |
mem_we <= we_i and stb_i and cyc_i; |
tech_ram: ram |
generic map ( |
data_width => data_width, |
addr_width => addr_width |
) |
port map ( |
clk => clk_i, |
we => mem_we, |
addr => adr_i, |
d_in => dat_i, |
d_out => mem_dat_o |
); |
|
dat_o_gen: for i in dat_o'RANGE generate |
dat_o(i) <= (mem_dat_o(i) and stb_i and cyc_i and not we_i) or (dat_oi(i) and not (stb_i and cyc_i and not we_i)); |
end generate; |
ack_o <= ('1' and stb_i and cyc_i) or (ack_oi and not (stb_i and cyc_i)); |
end wb_ram; |
|
/wb_vga/trunk/wb_tk/wb_test.vhd
0,0 → 1,345
-- |
-- Wishbone bus tester utilities. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/04/17 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
-- |
-- ELEMENTS: |
-- procedure wr_chk_val: writes a value, reads it back an checks if it's the same |
-- procedure wr_val: writes a value |
-- procedure rd_val: reads a value |
-- procedure chk_val: checks (after read) a value |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
library synopsys; |
use synopsys.std_logic_arith.all; |
|
package wb_test is |
procedure wr_chk_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in STD_LOGIC_VECTOR; |
constant data: in STD_LOGIC_VECTOR |
); |
procedure wr_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in STD_LOGIC_VECTOR; |
constant data: in STD_LOGIC_VECTOR |
); |
procedure rd_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in STD_LOGIC_VECTOR; |
variable data: out STD_LOGIC_VECTOR |
); |
procedure chk_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in STD_LOGIC_VECTOR; |
constant data: in STD_LOGIC_VECTOR |
); |
|
|
procedure wr_chk_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in integer; |
constant data: in STD_LOGIC_VECTOR |
); |
procedure wr_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in integer; |
constant data: in STD_LOGIC_VECTOR |
); |
procedure rd_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in integer; |
variable data: out STD_LOGIC_VECTOR |
); |
procedure chk_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in integer; |
constant data: in STD_LOGIC_VECTOR |
); |
end wb_test; |
|
|
package body wb_test is |
procedure wr_chk_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in STD_LOGIC_VECTOR; |
constant data: in STD_LOGIC_VECTOR |
) is |
variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0'); |
variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U'); |
begin |
adr_i <= adr_zero; |
dat_i <= dat_undef; |
stb_i <= '0'; |
we_i <= '0'; |
cyc_i <= '0'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
adr_i <= addr; |
dat_i <= data; |
cyc_i <= '1'; |
stb_i <= '1'; |
we_i <= '1'; |
wait until clk_i'EVENT and clk_i = '1' and ack_o = '1'; |
adr_i <= adr_zero; |
dat_i <= dat_undef; |
cyc_i <= '0'; |
stb_i <= '0'; |
we_i <= '0'; |
wait until clk_i'EVENT and clk_i = '1'; |
adr_i <= addr; |
dat_i <= dat_undef; |
cyc_i <= '1'; |
stb_i <= '1'; |
we_i <= '0'; |
wait until clk_i'EVENT and clk_i = '1' and ack_o = '1'; |
assert dat_o = data report "Value does not match!" severity ERROR; |
adr_i <= adr_zero; |
stb_i <= '0'; |
cyc_i <= '0'; |
end procedure; |
|
procedure wr_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in STD_LOGIC_VECTOR; |
constant data: in STD_LOGIC_VECTOR |
) is |
variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0'); |
variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U'); |
begin |
adr_i <= adr_zero; |
dat_i <= dat_undef; |
stb_i <= '0'; |
we_i <= '0'; |
cyc_i <= '0'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
adr_i <= addr; |
dat_i <= data; |
cyc_i <= '1'; |
stb_i <= '1'; |
we_i <= '1'; |
wait until clk_i'EVENT and clk_i = '1' and ack_o = '1'; |
adr_i <= adr_zero; |
dat_i <= dat_undef; |
cyc_i <= '0'; |
stb_i <= '0'; |
we_i <= '0'; |
end procedure; |
|
procedure rd_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in STD_LOGIC_VECTOR; |
variable data: out STD_LOGIC_VECTOR |
) is |
variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0'); |
variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U'); |
begin |
adr_i <= adr_zero; |
dat_i <= dat_undef; |
cyc_i <= '0'; |
stb_i <= '0'; |
we_i <= '0'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
adr_i <= addr; |
dat_i <= dat_undef; |
cyc_i <= '1'; |
stb_i <= '1'; |
we_i <= '0'; |
wait until clk_i'EVENT and clk_i = '1' and ack_o = '1'; |
data := dat_o; |
adr_i <= adr_zero; |
stb_i <= '0'; |
cyc_i <= '0'; |
end procedure; |
|
procedure chk_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in STD_LOGIC_VECTOR; |
constant data: in STD_LOGIC_VECTOR |
) is |
variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0'); |
variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U'); |
begin |
adr_i <= adr_zero; |
dat_i <= dat_undef; |
cyc_i <= '0'; |
stb_i <= '0'; |
we_i <= '0'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
adr_i <= addr; |
dat_i <= dat_undef; |
cyc_i <= '1'; |
stb_i <= '1'; |
we_i <= '0'; |
wait until clk_i'EVENT and clk_i = '1' and ack_o = '1'; |
assert dat_o = data report "Value does not match!" severity ERROR; |
adr_i <= adr_zero; |
stb_i <= '0'; |
cyc_i <= '0'; |
end procedure; |
|
procedure wr_chk_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in integer; |
constant data: in STD_LOGIC_VECTOR |
) is |
variable sadr: std_logic_vector(adr_i'RANGE); |
begin |
sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1); |
wr_chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data); |
end procedure; |
procedure wr_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in integer; |
constant data: in STD_LOGIC_VECTOR |
) is |
variable sadr: std_logic_vector(adr_i'RANGE); |
begin |
sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1); |
wr_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data); |
end procedure; |
procedure rd_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in integer; |
variable data: out STD_LOGIC_VECTOR |
) is |
variable sadr: std_logic_vector(adr_i'RANGE); |
begin |
sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1); |
rd_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data); |
end procedure; |
procedure chk_val( |
signal clk_i: in STD_LOGIC; |
signal adr_i: out STD_LOGIC_VECTOR; |
signal dat_o: in STD_LOGIC_VECTOR; |
signal dat_i: out STD_LOGIC_VECTOR; |
signal we_i: out STD_LOGIC; |
signal cyc_i: out std_logic; |
signal stb_i: out STD_LOGIC; |
signal ack_o: in STD_LOGIC; |
constant addr: in integer; |
constant data: in STD_LOGIC_VECTOR |
) is |
variable sadr: std_logic_vector(adr_i'RANGE); |
begin |
sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1); |
chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data); |
end procedure; |
|
end package body wb_test; |
|
/wb_vga/trunk/wb_tk/technology.vhd
0,0 → 1,431
-- |
-- Technology mapping library. ALTERA edition. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
library exemplar; |
use exemplar.exemplar_1164.all; |
|
package technology is |
function add_one(inp : std_logic_vector) return std_logic_vector; |
function is_zero(inp : std_logic_vector) return boolean; |
function sl(l: std_logic_vector; r: integer) return std_logic_vector; |
-- procedure inc(data : inout std_logic_vector); |
function "+"(op_l, op_r: std_logic_vector) return std_logic_vector; |
function log2(inp : integer) return integer; |
function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer; |
function size2bits(inp : integer) return integer; |
function max(a : integer; b: integer) return integer; |
function min2(a : integer; b: integer) return integer; |
function equ(a : std_logic_vector; b : integer) return boolean; |
|
component d_ff is |
port ( d : in STD_LOGIC; |
clk: in STD_LOGIC; |
ena: in STD_LOGIC := '1'; |
clr: in STD_LOGIC := '0'; |
pre: in STD_LOGIC := '0'; |
q : out STD_LOGIC |
); |
end component; |
component fifo is |
generic (fifo_width : positive; |
used_width : positive; |
fifo_depth : positive |
); |
port (d_in : in std_logic_vector(fifo_width-1 downto 0); |
clk : in std_logic; |
wr : in std_logic; |
rd : in std_logic; |
a_clr : in std_logic := '0'; |
s_clr : in std_logic := '0'; |
d_out : out std_logic_vector(fifo_width-1 downto 0); |
used : out std_logic_vector(used_width-1 downto 0); |
full : out std_logic; |
empty : out std_logic |
); |
end component; |
end technology; |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
library exemplar; |
use exemplar.exemplar_1164.all; |
library synopsys; |
use synopsys.std_logic_arith.all; |
|
package body technology is |
function "+"(op_l, op_r: std_logic_vector) return std_logic_vector is |
begin |
return exemplar_1164."+"(op_l, op_r); |
end; |
|
function add_one(inp : std_logic_vector) return std_logic_vector is |
variable one: std_logic_vector(inp'RANGE) := (others => '0'); |
begin |
one(0) := '1'; |
return exemplar_1164."+"(inp,one); |
end; |
|
function is_zero(inp : std_logic_vector) return boolean is |
variable zero: std_logic_vector(inp'RANGE) := (others => '0'); |
begin |
return (inp = zero); |
end; |
|
function sl(l: std_logic_vector; r: integer) return std_logic_vector is |
begin |
return exemplar_1164.sl(l,r); |
end; |
-- procedure inc(data : inout std_logic_vector) is |
-- begin |
-- data := addone(data); |
-- end; |
function max(a : integer; b: integer) return integer is |
begin |
if (a > b) then return a; end if; |
return b; |
end; |
|
function min2(a : integer; b: integer) return integer is |
begin |
if (a < b) then return a; end if; |
return b; |
end; |
|
function log2(inp : integer) return integer is |
begin |
if (inp < 1) then return 0; end if; |
if (inp < 2) then return 0; end if; |
if (inp < 4) then return 1; end if; |
if (inp < 8) then return 2; end if; |
if (inp < 16) then return 3; end if; |
if (inp < 32) then return 4; end if; |
if (inp < 64) then return 5; end if; |
if (inp < 128) then return 6; end if; |
if (inp < 256) then return 7; end if; |
if (inp < 512) then return 8; end if; |
if (inp < 1024) then return 9; end if; |
if (inp < 2048) then return 10; end if; |
if (inp < 4096) then return 11; end if; |
if (inp < 8192) then return 12; end if; |
if (inp < 16384) then return 13; end if; |
if (inp < 32768) then return 14; end if; |
if (inp < 65538) then return 15; end if; |
return 16; |
end; |
|
function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer is |
begin |
if (in_bus = out_bus) then return 0; end if; |
if (in_bus < out_bus) then return -log2(out_bus/in_bus); end if; |
if (in_bus > out_bus) then return log2(in_bus/out_bus); end if; |
end; |
|
function size2bits(inp : integer) return integer is |
begin |
if (inp < 1) then return 1; end if; |
if (inp < 2) then return 1; end if; |
if (inp < 4) then return 2; end if; |
if (inp < 8) then return 3; end if; |
if (inp < 16) then return 4; end if; |
if (inp < 32) then return 5; end if; |
if (inp < 64) then return 6; end if; |
if (inp < 128) then return 7; end if; |
if (inp < 256) then return 8; end if; |
if (inp < 512) then return 9; end if; |
if (inp < 1024) then return 10; end if; |
if (inp < 2048) then return 11; end if; |
if (inp < 4096) then return 12; end if; |
if (inp < 8192) then return 13; end if; |
if (inp < 16384) then return 14; end if; |
if (inp < 32768) then return 15; end if; |
if (inp < 65538) then return 16; end if; |
return 17; |
end; |
|
function equ(a : std_logic_vector; b : integer) return boolean is |
variable b_s : std_logic_vector(a'RANGE); |
begin |
b_s := CONV_STD_LOGIC_VECTOR(b,a'HIGH+1); |
return (a = b_s); |
end; |
|
end package body technology; |
|
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library exemplar; |
use exemplar.exemplar_1164.all; |
|
library lpm; |
use lpm.all; |
|
entity fifo is |
generic (fifo_width : positive; |
used_width : positive; |
fifo_depth : positive |
); |
port (d_in : in std_logic_vector(fifo_width-1 downto 0); |
clk : in std_logic; |
wr : in std_logic; |
rd : in std_logic; |
a_clr : in std_logic := '0'; |
s_clr : in std_logic := '0'; |
d_out : out std_logic_vector(fifo_width-1 downto 0); |
used : out std_logic_vector(used_width-1 downto 0); |
full : out std_logic; |
empty : out std_logic |
); |
end fifo; |
|
architecture altera of fifo is |
component lpm_fifo |
generic (LPM_WIDTH : positive; |
LPM_WIDTHU : positive; |
LPM_NUMWORDS : positive; |
LPM_SHOWAHEAD : string := "OFF"; |
LPM_TYPE : string := "LPM_FIFO"; |
LPM_HINT : string := "UNUSED"); |
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0); |
CLOCK : in std_logic; |
WRREQ : in std_logic; |
RDREQ : in std_logic; |
ACLR : in std_logic; |
SCLR : in std_logic; |
Q : out std_logic_vector(LPM_WIDTH-1 downto 0); |
USEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0); |
FULL : out std_logic; |
EMPTY : out std_logic); |
end component; |
begin |
altera_fifo: lpm_fifo |
generic map ( |
LPM_WIDTH => fifo_width, |
LPM_WIDTHU => used_width, |
LPM_NUMWORDS => fifo_depth, |
LPM_SHOWAHEAD => "OFF", |
LPM_TYPE => "LPM_FIFO", |
LPM_HINT => "UNUSED" |
) |
port map ( |
DATA => d_in, |
CLOCK => clk, |
WRREQ => wr, |
RDREQ => rd, |
ACLR => a_clr, |
SCLR => s_clr, |
Q => d_out, |
USEDW => used, |
FULL => full, |
EMPTY => empty |
); |
end altera; |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library exemplar; |
use exemplar.exemplar_1164.all; |
|
library lpm; |
use lpm.all; |
|
entity ram is |
generic ( |
data_width : positive; |
addr_width : positive |
); |
port ( |
clk : in std_logic; |
we : in std_logic; |
addr : in std_logic_vector(addr_width-1 downto 0); |
d_in : in std_logic_vector(data_width-1 downto 0); |
d_out : out std_logic_vector(data_width-1 downto 0) |
); |
end ram; |
|
architecture altera of ram is |
component lpm_ram_dp |
generic ( |
lpm_width: positive; |
lpm_widthad: positive; |
lpm_numwords: natural := 0; |
lpm_type: string := "lpm_ram_dp"; |
lpm_indata: string := "REGISTERED"; |
lpm_outdata: string := "UNREGISTERED"; |
lpm_rdaddress_control: string := "REGISTERED"; |
lpm_wraddress_control: string := "REGISTERED"; |
lpm_file: string := "UNUSED"; |
lpm_hint: string := "UNUSED" |
); |
port ( |
rdaddress, wraddress: in std_logic_vector(lpm_widthad-1 downto 0); |
rdclock, wrclock: in std_logic := '0'; |
rden, rdclken, wrclken: in std_logic := '1'; |
wren: in std_logic; |
data: in std_logic_vector(lpm_width-1 downto 0); |
q: out std_logic_vector(lpm_width-1 downto 0) |
); |
end component; |
begin |
altera_ram: lpm_ram_dp |
generic map ( |
lpm_width => data_width, |
lpm_widthad => addr_width, |
lpm_numwords => 2 ** addr_width, |
lpm_type => "lpm_ram_dp", |
lpm_indata => "REGISTERED", |
lpm_wraddress_control => "REGISTERED", |
lpm_outdata => "UNREGISTERED", |
lpm_rdaddress_control => "UNREGISTERED", |
lpm_file => "UNUSED", |
lpm_hint => "UNUSED" |
) |
port map ( |
-- rdclock => clk, |
rdclken => '1', |
rdaddress => addr, |
q => d_out, |
rden => '1', |
|
wrclock => clk, |
wrclken => '1', |
wraddress => addr, |
data => d_in, |
wren => we |
); |
end altera; |
|
|
|
|
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library exemplar; |
use exemplar.exemplar_1164.all; |
|
library lpm; |
use lpm.all; |
|
entity dpram is |
generic ( |
data_width : positive; |
addr_width : positive |
); |
port ( |
clk : in std_logic; |
|
r_d_out : out std_logic_vector(data_width-1 downto 0); |
r_rd : in std_logic; |
r_clk_en : in std_logic; |
r_addr : in std_logic_vector(addr_width-1 downto 0); |
|
w_d_in : in std_logic_vector(data_width-1 downto 0); |
w_wr : in std_logic; |
w_clk_en : in std_logic; |
w_addr : in std_logic_vector(addr_width-1 downto 0) |
); |
end dpram; |
|
architecture altera of dpram is |
component lpm_ram_dp |
generic ( |
lpm_width: positive; |
lpm_widthad: positive; |
lpm_numwords: natural := 0; |
lpm_type: string := "lpm_ram_dp"; |
lpm_indata: string := "REGISTERED"; |
lpm_outdata: string := "UNREGISTERED"; |
lpm_rdaddress_control: string := "REGISTERED"; |
lpm_wraddress_control: string := "REGISTERED"; |
lpm_file: string := "UNUSED"; |
lpm_hint: string := "UNUSED" |
); |
port ( |
rdaddress, wraddress: in std_logic_vector(lpm_widthad-1 downto 0); |
rdclock, wrclock: in std_logic := '0'; |
rden, rdclken, wrclken: in std_logic := '1'; |
wren: in std_logic; |
data: in std_logic_vector(lpm_width-1 downto 0); |
q: out std_logic_vector(lpm_width-1 downto 0) |
); |
end component; |
begin |
altera_ram: lpm_ram_dp |
generic map ( |
lpm_width => data_width, |
lpm_widthad => addr_width, |
lpm_numwords => 2 ** addr_width, |
lpm_type => "lpm_ram_dp", |
lpm_indata => "REGISTERED", |
lpm_wraddress_control => "REGISTERED", |
lpm_outdata => "UNREGISTERED", |
lpm_rdaddress_control => "UNREGISTERED", |
lpm_file => "UNUSED", |
lpm_hint => "UNUSED" |
) |
port map ( |
-- rdclock => clk, |
rdclken => r_clk_en, |
rdaddress => r_addr, |
q => r_d_out, |
rden => r_rd, |
|
wrclock => clk, |
wrclken => w_clk_en, |
wraddress => w_addr, |
data => w_d_in, |
wren => w_wr |
); |
end altera; |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library altera_exemplar; |
use altera_exemplar.all; |
|
entity d_ff is |
port ( d : in STD_LOGIC; |
clk: in STD_LOGIC; |
ena: in STD_LOGIC := '1'; |
clr: in STD_LOGIC := '0'; |
pre: in STD_LOGIC := '0'; |
q : out STD_LOGIC |
); |
end d_ff; |
|
architecture altera of d_ff is |
component dffe |
port ( D : in STD_LOGIC; |
CLK: in STD_LOGIC; |
ENA: in STD_LOGIC; |
CLRN: in STD_LOGIC; |
PRN: in STD_LOGIC; |
Q : out STD_LOGIC); |
end component; |
signal clrn,prn: std_logic; |
begin |
clrn <= not clr; |
prn <= not pre; |
ff: dffe port map ( |
D => d, |
CLK => clk, |
ENA => ena, |
CLRN => clrn, |
PRN => prn, |
Q => q |
); |
end altera; |
|
-- Sythetizer library. Contains STD_LOGIC arithmetics |
|
/wb_vga/trunk/wb_tk/wb_out_reg.vhd
0,0 → 1,94
-- |
-- Wishbone bus toolkit. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
-- |
-- ELEMENTS: |
-- wb_out_reg: Wishbone bus compatible output register. |
|
------------------------------------------------------------------------------- |
-- |
-- wb_out_reg |
-- |
------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.STD_LOGIC_UNSIGNED.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
|
entity wb_out_reg is |
generic ( |
width : positive := 8; |
bus_width: positive := 8; |
offset: integer := 0 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic; |
rst_val: std_logic_vector(width-1 downto 0) := (others => '0'); |
|
cyc_i: in std_logic := '1'; |
stb_i: in std_logic; |
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1'); |
we_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0'); |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
q: out std_logic_vector (width-1 downto 0) |
); |
end wb_out_reg; |
|
architecture wb_out_reg of wb_out_reg is |
signal content : std_logic_vector (width-1 downto 0); |
begin |
-- output bus handling with logic |
gen_dat_o: process is |
variable rd_sel: std_logic; |
variable adr: integer; |
variable reg_i: integer; |
begin |
wait on dat_oi, we_i, stb_i, content, adr_i, cyc_i, sel_i; |
rd_sel := cyc_i and stb_i and not we_i; |
for i in dat_i'RANGE loop |
adr := CONV_INTEGER(adr_i); |
reg_i := i-offset+adr*bus_width; |
if ((reg_i >= 0) and (reg_i < width) and (sel_i(i/8) = '1')) then |
dat_o(i) <= (dat_oi(i) and not rd_sel) or (content(reg_i) and rd_sel); |
else |
dat_o(i) <= dat_oi(i); |
end if; |
end loop; |
end process; |
|
-- this item never generates any wait-states |
ack_o <= stb_i or ack_oi; |
|
reg: process is |
variable adr: integer; |
variable reg_i: integer; |
begin |
wait until clk_i'EVENT and clk_i='1'; |
if (rst_i = '1') then |
content <= rst_val; |
else |
if (stb_i = '1' and cyc_i = '1' and we_i = '1') then |
for i in dat_i'RANGE loop |
adr := CONV_INTEGER(adr_i); |
reg_i := i-offset+adr*bus_width; |
if ((reg_i >= 0) and (reg_i < width) and (sel_i(i/8) = '1')) then |
content(reg_i) <= dat_i(i); |
end if; |
end loop; |
end if; |
end if; |
end process; |
q <= content; |
end wb_out_reg; |
/wb_vga/trunk/wb_tk/Makefile
0,0 → 1,2
all: |
bash compile.sh |
/wb_vga/trunk/wb_tk/wb_bus_dnsize.vhd
0,0 → 1,138
-- |
-- Wishbone bus toolkit. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
-- |
-- ELEMENTS: |
-- wb_bus_dnsize: bus downsizer. |
-- doesn't split access cycles so granularity on the input bus must not be greater than |
-- the width of the output bus. |
|
------------------------------------------------------------------------------- |
-- |
-- wb_bus_upsize |
-- |
------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.STD_LOGIC_UNSIGNED.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
|
library synopsys; |
use synopsys.std_logic_arith.all; |
|
entity wb_bus_dnsize is |
generic ( |
m_bus_width: positive := 32; -- master bus width |
m_addr_width: positive := 20; -- master bus width |
s_bus_width: positive := 16; -- slave bus width |
s_addr_width: positive := 21; -- master bus width |
little_endien: boolean := true -- if set to false, big endien |
); |
port ( |
-- clk_i: in std_logic; |
-- rst_i: in std_logic := '0'; |
|
-- Master bus interface |
m_adr_i: in std_logic_vector (m_addr_width-1 downto 0); |
m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1'); |
m_dat_i: in std_logic_vector (m_bus_width-1 downto 0); |
m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-'); |
m_dat_o: out std_logic_vector (m_bus_width-1 downto 0); |
m_cyc_i: in std_logic; |
m_ack_o: out std_logic; |
m_ack_oi: in std_logic := '-'; |
m_err_o: out std_logic; |
m_err_oi: in std_logic := '-'; |
m_rty_o: out std_logic; |
m_rty_oi: in std_logic := '-'; |
m_we_i: in std_logic; |
m_stb_i: in std_logic; |
|
-- Slave bus interface |
s_adr_o: out std_logic_vector (s_addr_width-1 downto 0); |
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0); |
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0); |
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0); |
s_cyc_o: out std_logic; |
s_ack_i: in std_logic; |
s_err_i: in std_logic := '-'; |
s_rty_i: in std_logic := '-'; |
s_we_o: out std_logic; |
s_stb_o: out std_logic |
); |
end wb_bus_dnsize; |
|
architecture wb_bus_dnsize of wb_bus_dnsize is |
constant addr_diff: integer := log2(m_bus_width/s_bus_width); |
constant mux_mask: integer := ((m_bus_width / 8)-1) - ((s_bus_width/8)-1); |
signal i_m_dat_o: std_logic_vector(m_bus_width-1 downto 0); |
signal mux_sel: std_logic_vector(log2(m_sel_i'HIGH+1)-1 downto 0); |
signal i_mux_sel: integer := 0; |
|
function prior_decode(inp: std_logic_vector) return integer is |
begin |
-- variable ret: std_logic_vector(log2(inp'HIGH)-1 downto 0) := (others = '1'); |
for i in inp'HIGH downto 0 loop |
if (inp(i) = '1') then |
return i; |
end if; |
end loop; |
return inp'HIGH; |
end; |
begin |
assert (s_addr_width = m_addr_width+addr_diff) report "Address widths are not consistent" severity FAILURE; |
|
-- Reconstructing address bits (mux_sel) |
compute_mux_sel: process is |
variable i: integer; |
begin |
wait on m_sel_i; |
i := prior_decode(m_sel_i); |
mux_sel <= CONV_STD_LOGIC_VECTOR(i,log2(m_sel_i'HIGH+1)) and CONV_STD_LOGIC_VECTOR(mux_mask,log2(m_sel_i'HIGH+1)); |
end process; |
i_mux_sel <= CONV_INTEGER(mux_sel); |
|
|
-- create slave address bus |
s_adr_o(s_addr_width-1 downto addr_diff) <= m_adr_i; |
s_adr_o_gen: process is |
variable all_ones: std_logic_vector(addr_diff-1 downto 0) := (others => '1'); |
begin |
wait on mux_sel(mux_sel'HIGH downto mux_sel'HIGH-addr_diff+1); |
if (little_endien) then |
s_adr_o(addr_diff-1 downto 0) <= mux_sel(mux_sel'HIGH downto mux_sel'HIGH-addr_diff+1); |
else |
s_adr_o(addr_diff-1 downto 0) <= all_ones-mux_sel(mux_sel'HIGH downto mux_sel'HIGH-addr_diff+1); |
end if; |
end process; |
|
-- create output byte select signals |
s_sel_o <= m_sel_i(i_mux_sel+(s_bus_width/8)-1 downto i_mux_sel); |
|
|
s_we_o <= m_we_i; |
m_ack_o <= (m_stb_i and s_ack_i) or (not m_stb_i and m_ack_oi); |
m_err_o <= (m_stb_i and s_err_i) or (not m_stb_i and m_err_oi); |
m_rty_o <= (m_stb_i and s_rty_i) or (not m_stb_i and m_rty_oi); |
s_stb_o <= m_stb_i; |
s_cyc_o <= m_cyc_i; |
|
-- Multiplex data-bus down to the slave width |
s_dat_o <= m_dat_i((i_mux_sel)*8-1+s_bus_width downto (i_mux_sel)*8); |
|
m_dat_o_mux: process is |
begin |
wait on m_dat_oi, s_dat_i, i_mux_sel, m_stb_i, m_we_i; |
m_dat_o <= m_dat_oi; |
if (m_stb_i = '1' and m_we_i = '0') then |
m_dat_o((i_mux_sel)*8-1+s_bus_width downto (i_mux_sel)*8) <= s_dat_i; |
end if; |
end process; |
end wb_bus_dnsize; |
|
/wb_vga/trunk/TestBench/vga_core_v2_TB.vhd
0,0 → 1,459
library ieee,exemplar; |
use ieee.std_logic_1164.all; |
use exemplar.exemplar_1164.all; |
use ieee.std_logic_unsigned.all; |
library synopsys; |
use synopsys.std_logic_arith.all; |
|
library wb_tk; |
use wb_tk.wb_test.all; |
|
library wb_vga; |
use wb_vga.all; |
use wb_vga.constants.all; |
|
entity vga_core_v2_tb is |
generic ( |
v_dat_width: positive := 16; |
v_adr_width : positive := 12; |
cpu_dat_width: positive := 8; |
cpu_adr_width: positive := 12; |
-- cpu_dat_width: positive := 16; |
-- cpu_adr_width: positive := 11; |
fifo_size: positive := 256; |
accel_size: positive := 9; |
v_pal_size: positive := 8; |
v_pal_width: positive := 16 |
); |
end vga_core_v2_tb; |
|
architecture TB of vga_core_v2_tb is |
-- Component declaration of the tested unit |
component vga_core_v2 |
generic ( |
v_dat_width: positive := v_dat_width; |
v_adr_width : positive := v_adr_width; |
cpu_dat_width: positive := cpu_dat_width; |
cpu_adr_width: positive := cpu_adr_width; |
fifo_size: positive := fifo_size; |
accel_size: positive := accel_size; |
v_pal_size: positive := v_pal_size; |
v_pal_width: positive := v_pal_width |
); |
port ( |
clk_i: in std_logic; |
clk_en: in std_logic := '1'; |
rst_i: in std_logic := '0'; |
|
-- CPU bus interface |
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
cyc_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic; |
err_o: out std_logic; |
err_oi: in std_logic; |
we_i: in std_logic; |
accel_stb_i: in std_logic; |
pal_stb_i: in std_logic; |
reg_stb_i: in std_logic; |
adr_i: in std_logic_vector (cpu_adr_width-1 downto 0); |
sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
|
-- video memory interface |
v_adr_o: out std_logic_vector (v_adr_width-1 downto 0); |
v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0); |
v_dat_i: in std_logic_vector (v_dat_width-1 downto 0); |
v_dat_o: out std_logic_vector (v_dat_width-1 downto 0); |
v_cyc_o: out std_logic; |
v_ack_i: in std_logic; |
v_we_o: out std_logic; |
v_stb_o: out std_logic; |
|
-- sync blank and video signal outputs |
h_sync: out std_logic; |
h_blank: out std_logic; |
v_sync: out std_logic; |
v_blank: out std_logic; |
h_tc: out std_logic; |
v_tc: out std_logic; |
blank: out std_logic; |
video_out: out std_logic_vector (v_pal_size-1 downto 0); -- video output binary signal (unused bits are forced to 0) |
true_color_out: out std_logic_vector (v_pal_width-1 downto 0) -- true-color video output |
); |
end component; |
|
signal clk_i: std_logic; |
signal clk_en: std_logic := '1'; |
signal rst_i: std_logic := '0'; |
|
-- CPU bus interface |
signal dat_i: std_logic_vector (cpu_dat_width-1 downto 0); |
signal dat_oi: std_logic_vector (cpu_dat_width-1 downto 0); |
signal dat_o: std_logic_vector (cpu_dat_width-1 downto 0); |
signal cyc_i: std_logic; |
signal ack_o: std_logic; |
signal ack_oi: std_logic; |
signal err_o: std_logic; |
signal err_oi: std_logic; |
signal we_i: std_logic; |
signal accel_stb_i: std_logic; |
signal pal_stb_i: std_logic; |
signal reg_stb_i: std_logic; |
signal adr_i: std_logic_vector (cpu_adr_width-1 downto 0); |
signal sel_i: std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
|
-- video memory interface |
signal v_adr_o: std_logic_vector (v_adr_width-1 downto 0); |
signal v_sel_o: std_logic_vector ((v_dat_width/8)-1 downto 0); |
signal v_dat_i: std_logic_vector (v_dat_width-1 downto 0); |
signal v_dat_o: std_logic_vector (v_dat_width-1 downto 0); |
signal v_cyc_o: std_logic; |
signal v_ack_i: std_logic; |
signal v_we_o: std_logic; |
signal v_stb_o: std_logic; |
|
-- sync blank and video signal outputs |
signal h_sync: std_logic; |
signal h_blank: std_logic; |
signal v_sync: std_logic; |
signal v_blank: std_logic; |
signal h_tc: std_logic; |
signal v_tc: std_logic; |
signal blank: std_logic; |
signal video_out: std_logic_vector (v_pal_size-1 downto 0); -- video output binary signal (unused bits are forced to 0) |
signal true_color_out: std_logic_vector (v_pal_width-1 downto 0); -- true-color video output |
|
constant reg_total0 : integer := 0; |
constant reg_total1 : integer := 1; |
constant reg_total2 : integer := 2; |
constant reg_total3 : integer := 3; |
constant reg_ofs0 : integer := 4; |
constant reg_ofs1 : integer := 5; |
constant reg_ofs2 : integer := 6; |
constant reg_ofs3 : integer := 7; |
|
constant reg_fifo_treshold : integer := 16; |
constant reg_bpp : integer := 17; |
constant reg_hbs : integer := 18; |
constant reg_hss : integer := 19; |
constant reg_hse : integer := 20; |
constant reg_htotal : integer := 21; |
constant reg_vbs : integer := 22; |
constant reg_vss : integer := 23; |
constant reg_vse : integer := 24; |
constant reg_vtotal : integer := 25; |
constant reg_pps : integer := 26; |
constant reg_sync_pol : integer := 27; |
|
constant reg_ws : integer := 32; |
constant reg_cur : integer := 40; |
constant reg_ext : integer := 44; |
|
constant val_total0 : std_logic_vector(7 downto 0) := "11111111"; |
constant val_total1 : std_logic_vector(7 downto 0) := "00000000"; |
constant val_total2 : std_logic_vector(7 downto 0) := "00000000"; |
constant val_total3 : std_logic_vector(7 downto 0) := "00000000"; |
constant val_ofs0 : std_logic_vector(7 downto 0) := "00000000"; |
constant val_ofs1 : std_logic_vector(7 downto 0) := "00000000"; |
constant val_ofs2 : std_logic_vector(7 downto 0) := "00000000"; |
constant val_ofs3 : std_logic_vector(7 downto 0) := "00000000"; |
constant val_fifo_treshold : std_logic_vector(7 downto 0) := "00000011"; |
constant val_bpp : std_logic_vector(7 downto 0) := "00000011"; |
constant val_hbs : std_logic_vector(7 downto 0) := "00000111"; |
constant val_hss : std_logic_vector(7 downto 0) := "00001000"; |
constant val_hse : std_logic_vector(7 downto 0) := "00001001"; |
constant val_htotal : std_logic_vector(7 downto 0) := "00001010"; |
constant val_vbs : std_logic_vector(7 downto 0) := "00000001"; |
constant val_vss : std_logic_vector(7 downto 0) := "00000010"; |
constant val_vse : std_logic_vector(7 downto 0) := "00000011"; |
constant val_vtotal : std_logic_vector(7 downto 0) := "00000100"; |
constant val_pps : std_logic_vector(7 downto 0) := "00000001"; |
constant val_sync_pol : std_logic_vector(7 downto 0) := "10000000"; |
constant val_ws : std_logic_vector(7 downto 0) := "00000010"; |
|
type data_array is array (integer range <>) of std_logic_vector(v_dat_width-1 downto 0);-- Memory Type |
signal mem_data : data_array(0 to (2** v_adr_width-1) ); -- Local data |
begin |
|
UUT : vga_core_v2 |
port map ( |
clk_i =>clk_i, |
clk_en =>clk_en, |
rst_i =>rst_i, |
|
-- CPU bus interface |
dat_i =>dat_i, |
dat_oi =>dat_oi, |
dat_o =>dat_o, |
cyc_i =>cyc_i, |
ack_o =>ack_o, |
ack_oi =>ack_oi, |
err_o =>err_o, |
err_oi =>err_oi, |
we_i =>we_i, |
accel_stb_i =>accel_stb_i, |
pal_stb_i =>pal_stb_i, |
reg_stb_i =>reg_stb_i, |
adr_i =>adr_i, |
sel_i =>sel_i, |
|
-- video memory interface |
v_adr_o =>v_adr_o, |
v_sel_o =>v_sel_o, |
v_dat_i =>v_dat_i, |
v_dat_o =>v_dat_o, |
v_cyc_o =>v_cyc_o, |
v_ack_i =>v_ack_i, |
v_we_o =>v_we_o, |
v_stb_o =>v_stb_o, |
|
-- sync blank and video outputs |
h_sync =>h_sync, |
h_blank =>h_blank, |
v_sync =>v_sync, |
v_blank =>v_blank, |
h_tc =>h_tc, |
v_tc =>v_tc, |
blank =>blank, |
video_out =>video_out, |
true_color_out=>true_color_out |
); |
|
-- Add your stimulus here ... |
|
clk_en <= '1'; |
-- Add your stimulus here ... |
clock: process is |
begin |
wait for 25 ns; |
clk_i <= '1'; |
wait for 25 ns; |
clk_i <= '0'; |
end process; |
|
ack_oi <= '1'; |
err_oi <= '1'; |
dat_oi <= (others => '0'); |
|
setup: process is |
begin |
sel_i <= (others => '1'); |
we_i <= '0'; |
reg_stb_i <= '0'; |
accel_stb_i <= '0'; |
pal_stb_i <= '0'; |
cyc_i <= '0'; |
rst_i <= '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
rst_i <= '0'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
|
if (cpu_dat_width = 8) then |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0 ,val_total0); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total1 ,val_total1); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2 ,val_total2); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total3 ,val_total3); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0 ,val_ofs0); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs1 ,val_ofs1); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs2 ,val_ofs2); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs3 ,val_ofs3); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws ,val_ws); |
|
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold ,val_fifo_treshold); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_bpp ,val_bpp); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs ,val_hbs); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hss ,val_hss); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse ,val_hse); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_htotal ,val_htotal); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs ,val_vbs); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vss ,val_vss); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse ,val_vse); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vtotal ,val_vtotal); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps ,val_pps); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_sync_pol ,val_sync_pol); |
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,0 ,"00000001"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,1 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,2 ,"00000010"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,3 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,4 ,"00000100"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,5 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,6 ,"00001000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,7 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,8 ,"00010000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,9 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,10 ,"00100000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,11 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,12 ,"01000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,13 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,14 ,"10000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,15 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,16 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,17 ,"00000001"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,18 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,19 ,"00000010"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,20 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,21 ,"00000100"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,22 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,23 ,"00001000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,24 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,25 ,"00010000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,26 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,27 ,"00100000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,28 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,29 ,"01000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,30 ,"00000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,31 ,"10000000"); |
end if; |
if (cpu_dat_width = 16) then |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0/2 ,val_total1 & val_total0); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2/2 ,val_total3 & val_total2); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0/2 ,val_ofs1 & val_ofs0); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs2/2 ,val_ofs3 & val_ofs2); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws/2 ,"00000000" & val_ws ); |
|
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold/2 ,val_bpp & val_fifo_treshold); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs/2 ,val_hss & val_hbs); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse/2 ,val_htotal & val_hse); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs/2 ,val_vss & val_vbs); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse/2 ,val_vtotal & val_vse); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps/2 ,val_sync_pol & val_pps); |
|
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,0 ,"0000000000000001"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,1 ,"0000000000000010"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,2 ,"0000000000000100"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,3 ,"0000000000001000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,4 ,"0000000000010000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,5 ,"0000000000100000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,6 ,"0000000001000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,7 ,"0000000010000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,8 ,"0000000100000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,9 ,"0000001000000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,10 ,"0000010000000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,11 ,"0000100000000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,12 ,"0001000000000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,13 ,"0010000000000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,14 ,"0100000000000000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,15 ,"1000000000000000"); |
|
wait for 90us; |
wait until clk_i'EVENT and clk_i = '1'; |
|
-- Set Cursor to 0 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2 ,"0000000000000000"); |
-- Accel index 0 is 0 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,0,"0000000000000000"); |
-- Accel index 1 is 1 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,1,"0000000000000001"); |
-- Accel index 2 is 3 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2,"0000000000000011"); |
-- Accel index 3 is -1 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,3,"1111111111111111"); |
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+0,"1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000"); |
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000000001"); |
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000"); |
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000001000"); |
|
-- Set Cursor to 16 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000010000"); |
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+0,"1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000"); |
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000010001"); |
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000"); |
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000011000"); |
|
-- Set Cursor to 0 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000000000"); |
|
|
end if; |
if (cpu_dat_width = 32) then |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0/4 ,val_total3 & val_total2 & val_total1 & val_total0); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0/4 ,val_ofs3 & val_ofs2 & val_ofs1 & val_ofs0); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws/4 ,"000000000000000000000000" & val_ws ); |
|
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold/4 ,val_hss & val_hbs & val_bpp & val_fifo_treshold); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse/4 ,val_vss & val_vbs & val_htotal & val_hse); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse/4 ,val_sync_pol & val_pps & val_vtotal & val_vse); |
end if; |
|
wait; |
end process; |
|
|
ram: process is |
-- type data_array is array (integer range <>) of std_logic_vector(v_dat_width-1 downto 0);-- Memory Type |
-- variable data : data_array(0 to (2** v_adr_width-1) ); -- Local data |
variable init: boolean := true; |
begin |
if (init) then |
for i in mem_data'RANGE loop |
mem_data(i) <= CONV_STD_LOGIC_VECTOR(i,v_dat_width); |
-- data(i) := (others => '0'); |
end loop; |
init := false; |
end if; |
|
wait on clk_i, v_cyc_o, v_stb_o, v_we_o, v_dat_o; |
if (v_cyc_o = '1' and v_stb_o = '1') then |
v_ack_i <= '1'; |
else |
v_ack_i <= '0'; |
end if; |
|
if (clk_i'EVENT and clk_i = '1' and v_cyc_o = '1' and v_stb_o = '1' and v_we_o = '1') then |
mem_data(CONV_INTEGER(v_adr_o)) <= v_dat_o; |
v_dat_i <= (others => 'U'); |
elsif (v_cyc_o = '1' and v_stb_o = '1' and v_we_o = '0') then |
v_dat_i <= mem_data(CONV_INTEGER(v_adr_o)); |
-- v_dat_i <= v_adr_o(v_dat_i'RANGE); |
else |
v_dat_i <= (others => 'U'); |
end if; |
end process; |
|
end TB; |
|
/wb_vga/trunk/TestBench/vga_chip_TB.vhd
0,0 → 1,299
library ieee,exemplar; |
use ieee.std_logic_1164.all; |
use exemplar.exemplar_1164.all; |
|
library wb_tk; |
use wb_tk.wb_test.all; |
|
library wb_vga; |
use wb_vga.all; |
use wb_vga.constants.all; |
|
entity vga_chip_tb is |
end vga_chip_tb; |
|
architecture TB of vga_chip_tb is |
-- Component declaration of the tested unit |
component vga_chip is |
port ( |
clk_i: in std_logic; |
clk_en: in std_logic := '1'; |
rst_i: in std_logic := '0'; |
|
-- CPU bus interface |
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
cyc_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic; |
we_i: in std_logic; |
vmem_stb_i: in std_logic; |
reg_stb_i: in std_logic; |
adr_i: in std_logic_vector (cpu_adr_width-1 downto 0); |
sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
|
-- video memory SRAM interface |
s_data : inout std_logic_vector(v_dat_width-1 downto 0); |
s_addr : out std_logic_vector(v_adr_width-1 downto 0); |
s_oen : out std_logic; |
s_wrhn : out std_logic; |
s_wrln : out std_logic; |
s_cen : out std_logic; |
|
-- sync blank and video signal outputs |
h_sync: out std_logic; |
h_blank: out std_logic; |
v_sync: out std_logic; |
v_blank: out std_logic; |
h_tc: out std_logic; |
v_tc: out std_logic; |
blank: out std_logic; |
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0) |
); |
end component; |
|
-- Stimulus signals - signals mapped to the input and inout ports of tested entity |
signal clk_i : std_logic; |
signal clk_en : std_logic; |
signal rst_i : std_logic; |
signal dat_i : std_logic_vector(cpu_dat_width-1 downto 0); |
signal dat_oi : std_logic_vector(cpu_dat_width-1 downto 0); |
signal cyc_i : std_logic; |
signal ack_oi : std_logic; |
signal we_i : std_logic; |
signal vmem_stb_i : std_logic; |
signal reg_stb_i : std_logic; |
signal adr_i : std_logic_vector(cpu_adr_width-1 downto 0); |
signal sel_i: std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
signal s_data : std_logic_vector(v_dat_width-1 downto 0); |
-- Observed signals - signals mapped to the output ports of tested entity |
signal dat_o : std_logic_vector(cpu_dat_width-1 downto 0); |
signal ack_o : std_logic; |
signal s_addr : std_logic_vector(v_adr_width-1 downto 0); |
signal s_oen : std_logic; |
signal s_wrhn : std_logic; |
signal s_wrln : std_logic; |
signal s_cen : std_logic; |
signal h_sync : std_logic; |
signal h_blank : std_logic; |
signal v_sync : std_logic; |
signal v_blank : std_logic; |
signal h_tc : std_logic; |
signal v_tc : std_logic; |
signal blank : std_logic; |
signal video_out : std_logic_vector(7 downto 0); |
|
constant reg_total0 : integer := 0; |
constant reg_total1 : integer := 1; |
constant reg_total2 : integer := 2; |
constant reg_total3 : integer := 3; |
constant reg_ofs0 : integer := 4; |
constant reg_ofs1 : integer := 5; |
constant reg_ofs2 : integer := 6; |
constant reg_ofs3 : integer := 7; |
|
constant reg_fifo_treshold : integer := 16; |
constant reg_bpp : integer := 17; |
constant reg_hbs : integer := 18; |
constant reg_hss : integer := 19; |
constant reg_hse : integer := 20; |
constant reg_htotal : integer := 21; |
constant reg_vbs : integer := 22; |
constant reg_vss : integer := 23; |
constant reg_vse : integer := 24; |
constant reg_vtotal : integer := 25; |
constant reg_pps : integer := 26; |
constant reg_sync_pol : integer := 27; |
|
constant reg_ws : integer := 32; |
|
constant val_total0 : std_logic_vector(7 downto 0) := "00001111"; |
constant val_total1 : std_logic_vector(7 downto 0) := "00000000"; |
constant val_total2 : std_logic_vector(7 downto 0) := "00000000"; |
constant val_total3 : std_logic_vector(7 downto 0) := "00000000"; |
constant val_ofs0 : std_logic_vector(7 downto 0) := "00000000"; |
constant val_ofs1 : std_logic_vector(7 downto 0) := "00000000"; |
constant val_ofs2 : std_logic_vector(7 downto 0) := "00000000"; |
constant val_ofs3 : std_logic_vector(7 downto 0) := "00000000"; |
constant val_fifo_treshold : std_logic_vector(7 downto 0) := "00000011"; |
constant val_bpp : std_logic_vector(7 downto 0) := "00000011"; |
constant val_hbs : std_logic_vector(7 downto 0) := "00000111"; |
constant val_hss : std_logic_vector(7 downto 0) := "00001000"; |
constant val_hse : std_logic_vector(7 downto 0) := "00001001"; |
constant val_htotal : std_logic_vector(7 downto 0) := "00001010"; |
constant val_vbs : std_logic_vector(7 downto 0) := "00000001"; |
constant val_vss : std_logic_vector(7 downto 0) := "00000010"; |
constant val_vse : std_logic_vector(7 downto 0) := "00000011"; |
constant val_vtotal : std_logic_vector(7 downto 0) := "00000100"; |
constant val_pps : std_logic_vector(7 downto 0) := "00000001"; |
constant val_sync_pol : std_logic_vector(7 downto 0) := "10000000"; |
constant val_ws : std_logic_vector(7 downto 0) := "00000010"; |
|
begin |
|
-- Unit Under Test port map |
UUT : vga_chip |
port map ( |
clk_i => clk_i, |
clk_en => clk_en, |
rst_i => rst_i, |
dat_i => dat_i, |
dat_oi => dat_oi, |
dat_o => dat_o, |
cyc_i => cyc_i, |
ack_o => ack_o, |
ack_oi => ack_oi, |
we_i => we_i, |
vmem_stb_i => vmem_stb_i, |
reg_stb_i => reg_stb_i, |
adr_i => adr_i, |
s_data => s_data, |
s_addr => s_addr, |
s_oen => s_oen, |
s_wrhn => s_wrhn, |
s_wrln => s_wrln, |
s_cen => s_cen, |
h_sync => h_sync, |
h_blank => h_blank, |
v_sync => v_sync, |
v_blank => v_blank, |
h_tc => h_tc, |
v_tc => v_tc, |
blank => blank, |
video_out => video_out |
); |
|
-- Add your stimulus here ... |
|
clk_en <= '1'; |
-- Add your stimulus here ... |
clock: process is |
begin |
wait for 25 ns; |
clk_i <= '1'; |
wait for 25 ns; |
clk_i <= '0'; |
end process; |
|
ack_oi <= '0'; |
dat_oi <= (others => '0'); |
|
setup: process is |
begin |
sel_i <= (others => '1'); |
we_i <= '0'; |
reg_stb_i <= '0'; |
vmem_stb_i <= '0'; |
cyc_i <= '0'; |
rst_i <= '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
rst_i <= '0'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
|
if (cpu_dat_width = 8) then |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0 ,val_total0); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total1 ,val_total1); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2 ,val_total2); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total3 ,val_total3); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0 ,val_ofs0); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs1 ,val_ofs1); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs2 ,val_ofs2); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs3 ,val_ofs3); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws ,val_ws); |
|
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold ,val_fifo_treshold); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_bpp ,val_bpp); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs ,val_hbs); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hss ,val_hss); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse ,val_hse); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_htotal ,val_htotal); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs ,val_vbs); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vss ,val_vss); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse ,val_vse); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vtotal ,val_vtotal); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps ,val_pps); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_sync_pol ,val_sync_pol); |
end if; |
if (cpu_dat_width = 16) then |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0/2 ,val_total1 & val_total0); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2/2 ,val_total3 & val_total2); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0/2 ,val_ofs1 & val_ofs0); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs2/2 ,val_ofs3 & val_ofs2); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws/2 ,"00000000" & val_ws ); |
|
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold/2 ,val_bpp & val_fifo_treshold); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs/2 ,val_hss & val_hbs); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse/2 ,val_htotal & val_hse); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs/2 ,val_vss & val_vbs); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse/2 ,val_vtotal & val_vse); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps/2 ,val_sync_pol & val_pps); |
end if; |
if (cpu_dat_width = 32) then |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0/4 ,val_total3 & val_total2 & val_total1 & val_total0); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0/4 ,val_ofs3 & val_ofs2 & val_ofs1 & val_ofs0); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws/4 ,"000000000000000000000000" & val_ws ); |
|
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold/4 ,val_hss & val_hbs & val_bpp & val_fifo_treshold); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse/4 ,val_vss & val_vbs & val_htotal & val_hse); |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse/4 ,val_sync_pol & val_pps & val_vtotal & val_vse); |
end if; |
|
wait; |
end process; |
|
s_ram: process is |
begin |
wait on s_data,s_addr,s_oen,s_wrhn,s_wrln,s_cen; |
if (s_cen = '0') then |
if (s_oen = '0') then |
s_data <= s_addr(v_dat_width-1 downto 0); |
elsif (s_wrhn = '0' or s_wrln = '0') then |
if (s_wrhn = '0') then |
else |
end if; |
else |
s_data <= (others => 'Z'); |
end if; |
end if; |
end process; |
|
end TB; |
|
configuration TB_vga_chip of vga_chip_tb is |
for TB |
for UUT : vga_chip |
use entity wb_vga.vga_chip(vga_chip); |
end for; |
end for; |
end TB_vga_chip; |
|
|
--configuration SYNTH_vga_chip of vga_chip_tb is |
-- for TB |
-- for UUT : vga_chip |
-- use entity work.vga_chip(ep1k30fc256_a1); |
-- end for; |
-- end for; |
--end SYNTH_vga_chip; |
-- |
-- |
/wb_vga/trunk/TestBench/palette_TB.vhd
0,0 → 1,163
library ieee,wb_tk,wb_vga; |
use ieee.NUMERIC_STD.all; |
use ieee.std_logic_1164.all; |
use wb_tk.technology.all; |
use wb_tk.wb_test.all; |
use wb_tk.all; |
use wb_vga.all; |
|
entity wb_pal_ram_tb is |
generic( |
cpu_dat_width: positive := 32; |
cpu_adr_width: positive := 8; |
v_dat_width: positive := 16; |
v_adr_width: positive := 8 |
); |
end wb_pal_ram_tb; |
|
architecture TB of wb_pal_ram_tb is |
component wb_pal_ram |
generic ( |
cpu_dat_width: positive := cpu_dat_width; |
cpu_adr_width: positive := cpu_adr_width; |
v_dat_width: positive := v_dat_width; |
v_adr_width: positive := v_adr_width |
); |
port ( |
-- Wishbone interface to CPU (write-only support) |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
adr_i: in std_logic_vector (cpu_adr_width-1 downto 0); |
-- sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
cyc_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
err_o: out std_logic; |
err_oi: in std_logic := '-'; |
-- rty_o: out std_logic; |
-- rty_oi: in std_logic := '-'; |
we_i: in std_logic; |
stb_i: in std_logic; |
-- Interface to the video output |
blank: in std_logic; |
v_dat_i: in std_logic_vector(v_adr_width-1 downto 0); |
v_dat_o: out std_logic_vector(v_dat_width-1 downto 0) |
); |
end component; |
|
-- Wishbone interface to CPU (write-only support) |
signal clk_i: std_logic; |
signal rst_i: std_logic := '0'; |
signal adr_i: std_logic_vector (cpu_adr_width-1 downto 0); |
signal dat_i: std_logic_vector (cpu_dat_width-1 downto 0); |
signal dat_oi: std_logic_vector (cpu_dat_width-1 downto 0) := (others => '-'); |
signal dat_o: std_logic_vector (cpu_dat_width-1 downto 0); |
signal cyc_i: std_logic; |
signal ack_o: std_logic; |
signal ack_oi: std_logic := '-'; |
signal err_o: std_logic; |
signal err_oi: std_logic := '-'; |
signal we_i: std_logic; |
signal stb_i: std_logic; |
-- Interface to the video output |
signal blank: std_logic; |
signal v_dat_i: std_logic_vector(v_adr_width-1 downto 0); |
signal v_dat_o: std_logic_vector(v_dat_width-1 downto 0); |
begin |
|
-- Unit Under Test port map |
UUT : wb_pal_ram |
port map ( |
clk_i => clk_i, |
rst_i => rst_i, |
adr_i => adr_i, |
dat_i => dat_i, |
dat_oi => dat_oi, |
dat_o => dat_o, |
cyc_i => cyc_i, |
ack_o => ack_o, |
ack_oi => ack_oi, |
err_o => err_o, |
err_oi => err_oi, |
we_i => we_i, |
stb_i => stb_i, |
|
blank => blank, |
v_dat_i => v_dat_i, |
v_dat_o => v_dat_o |
); |
|
clk: process is |
begin |
clk_i <= '0'; |
wait for 25ns; |
clk_i <= '1'; |
wait for 25ns; |
end process; |
|
reset: process is |
begin |
rst_i <= '1'; |
wait for 150ns; |
rst_i <= '0'; |
wait; |
end process; |
|
gen_v_output: process is |
variable addr: std_logic_vector(v_adr_width-1 downto 0) := (others => '0'); |
begin |
blank <= '0'; |
wait until clk_i'EVENT and clk_i = '1'; |
v_dat_i <= addr; |
-- if (addr = "1111") then |
-- blank <= '1'; |
-- wait until clk_i'EVENT and clk_i = '1'; |
-- addr := (v_adr_width'RANGE => '0'); |
-- else |
addr := add_one(addr); |
-- end if; |
end process; |
|
dat_oi <= (others => 'U'); |
ack_oi <= 'U'; |
err_oi <= 'U'; |
|
master: process is |
variable i: integer := 0; |
variable addr: std_logic_vector(cpu_adr_width-1 downto 0) := (others => '0'); |
variable data: std_logic_vector(cpu_dat_width-1 downto 0) := (others => '0'); |
begin |
we_i <= '0'; |
cyc_i <= '0'; |
stb_i <= '0'; |
adr_i <= (others => '0'); |
dat_i <= (others => '0'); |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
|
for i in 0 to 511 loop |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,addr,data); |
addr := add_one(addr); |
data := add_one(data); |
end loop; |
wait; |
end process; |
|
end TB; |
|
configuration TB_wb_pal_ram of wb_pal_ram_tb is |
for TB |
for UUT : wb_pal_ram |
use entity wb_vga.wb_pal_ram(wb_pal_ram); |
end for; |
end for; |
end TB_wb_pal_ram; |
|
/wb_vga/trunk/TestBench/accel_TB.vhd
0,0 → 1,226
library ieee,wb_tk,wb_vga; |
use ieee.NUMERIC_STD.all; |
use ieee.std_logic_1164.all; |
use wb_tk.technology.all; |
use wb_tk.wb_test.all; |
use wb_tk.all; |
use wb_vga.all; |
|
entity accel_tb is |
generic( |
accel_size : POSITIVE := 9; |
video_addr_width : POSITIVE := 20; |
video_data_width : POSITIVE := 16; |
data_width : POSITIVE := 16 ); |
end accel_tb; |
|
architecture TB of accel_tb is |
component accel |
generic( |
accel_size : POSITIVE := accel_size; |
video_addr_width : POSITIVE := video_addr_width; |
video_data_width : POSITIVE := video_data_width; |
data_width : POSITIVE := data_width |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- Slave interface to the CPU side |
we_i: in std_logic; |
cyc_i: in std_logic; |
sel_i: in std_logic_vector ((data_width/8)-1 downto 0) := (others => '1'); |
cur_stb_i: in std_logic; |
ext_stb_i: in std_logic; |
acc_stb_i: in std_logic; |
mem_stb_i: in std_logic; |
|
adr_i: in std_logic_vector(accel_size-1 downto 0); |
dat_i: in std_logic_vector(data_width-1 downto 0); |
dat_o: out std_logic_vector(data_width-1 downto 0); |
dat_oi: in std_logic_vector(data_width-1 downto 0); |
|
ack_o: out std_logic; |
ack_oi: in std_logic; |
|
-- Master interface to the video memory side. |
v_we_o: out std_logic; |
v_cyc_o: out std_logic; |
v_sel_o: out std_logic; |
|
v_adr_o: out std_logic_vector (video_addr_width-1 downto 0); |
v_dat_o: out std_logic_vector (video_data_width-1 downto 0); |
v_dat_i: in std_logic_vector (video_data_width-1 downto 0); |
|
v_ack_i: in std_logic |
); |
end component; |
|
-- Stimulus signals - signals mapped to the input and inout ports of tested entity |
signal clk_i : std_logic; |
signal rst_i : std_logic; |
signal we_i : std_logic; |
signal cyc_i : std_logic; |
signal sel_i: std_logic_vector ((data_width/8)-1 downto 0) := (others => '1'); |
signal cur_stb_i : std_logic; |
signal ext_stb_i : std_logic; |
signal acc_stb_i : std_logic; |
signal mem_stb_i : std_logic; |
signal adr_i : std_logic_vector((accel_size-1) downto 0); |
signal dat_i : std_logic_vector((data_width-1) downto 0); |
signal dat_oi : std_logic_vector((data_width-1) downto 0); |
signal ack_oi : std_logic; |
signal v_dat_i : std_logic_vector((video_data_width-1) downto 0); |
signal v_ack_i : std_logic; |
-- Observed signals - signals mapped to the output ports of tested entity |
signal dat_o : std_logic_vector((data_width-1) downto 0); |
signal ack_o : std_logic; |
signal v_we_o : std_logic; |
signal v_sel_o : std_logic; |
signal v_cyc_o : std_logic; |
signal v_adr_o : std_logic_vector((video_addr_width-1) downto 0); |
signal v_dat_o : std_logic_vector((video_data_width-1) downto 0); |
begin |
|
-- Unit Under Test port map |
UUT : accel |
port map |
(clk_i => clk_i, |
rst_i => rst_i, |
we_i => we_i, |
cyc_i => cyc_i, |
sel_i => sel_i, |
cur_stb_i => cur_stb_i, |
ext_stb_i => ext_stb_i, |
acc_stb_i => acc_stb_i, |
mem_stb_i => mem_stb_i, |
adr_i => adr_i, |
dat_i => dat_i, |
dat_o => dat_o, |
dat_oi => dat_oi, |
ack_o => ack_o, |
ack_oi => ack_oi, |
v_we_o => v_we_o, |
v_cyc_o => v_cyc_o, |
v_sel_o => v_sel_o, |
v_adr_o => v_adr_o, |
v_dat_o => v_dat_o, |
v_dat_i => v_dat_i, |
v_ack_i => v_ack_i ); |
|
clk: process is |
begin |
clk_i <= '0'; |
wait for 25ns; |
clk_i <= '1'; |
wait for 25ns; |
end process; |
|
reset: process is |
begin |
rst_i <= '1'; |
wait for 150ns; |
rst_i <= '0'; |
wait; |
end process; |
|
memory: process is |
begin |
v_ack_i <= '0'; |
v_dat_i <= (others => 'U'); |
if (v_sel_o /= '1') then wait until v_sel_o = '1'; end if; |
wait until clk_i'EVENT and clk_i = '1'; |
v_ack_i <= '1'; |
if (v_we_o = '1') then |
v_dat_i <= v_adr_o(v_dat_i'RANGE); |
else |
v_dat_i <= (others => 'U'); |
end if; |
wait until clk_i'EVENT and clk_i = '1'; |
wait for 15ns; |
end process; |
|
dat_oi <= (others => 'U'); |
ack_oi <= 'U'; |
|
master: process is |
variable init: boolean := true; |
begin |
if (init) then |
we_i <= '0'; |
cyc_i <= '0'; |
cur_stb_i <= '0'; |
ext_stb_i <= '0'; |
acc_stb_i <= '0'; |
mem_stb_i <= '0'; |
adr_i <= (others => '0'); |
dat_i <= (others => '0'); |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
wait until clk_i'EVENT and clk_i = '1'; |
|
-- Set Cursor to 0 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000000000"); |
-- Accel index 0 is 0 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000000","0000000000000000"); |
-- Accel index 1 is 1 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000001","0000000000000001"); |
-- Accel index 2 is 3 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000010","0000000000000011"); |
-- Accel index 3 is -1 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000011","1111111111111111"); |
end if; |
init := false; |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000000","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000"); |
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000000001"); |
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000"); |
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000001000"); |
|
-- Set Cursor to 16 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000010000"); |
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000000","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000"); |
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000010001"); |
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000"); |
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000"); |
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000011000"); |
|
-- Set Cursor to 0 |
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000000000"); |
|
wait; |
end process; |
|
end TB; |
|
configuration TB_accel of accel_tb is |
for TB |
for UUT : accel |
use entity wb_vga.accel(accel); |
end for; |
end for; |
end TB_accel; |
|
/wb_vga/trunk/mem_reader.vhd
0,0 → 1,348
-- |
-- File: mem_reader.vhd |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
|
entity mem_reader is |
generic ( |
v_mem_width: positive := 16; |
v_addr_width: positive:= 20; |
fifo_size: positive := 256; |
dual_scan_fifo_size: positive := 256 |
); |
port ( |
clk: in std_logic; |
clk_en: in std_logic; |
pix_clk_en: in std_logic; |
reset: in std_logic := '0'; |
|
v_mem_end: in std_logic_vector(v_addr_width-1 downto 0); -- video memory end address in words |
v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words |
fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold |
bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8 |
multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans |
|
-- Can be githces on it!!! Don't clock by it!!! |
high_prior: out std_logic; -- signals to the memory arbitrer to give high |
-- priority to the video engine |
v_mem_rd: out std_logic; -- video memory read request |
v_mem_rdy: in std_logic; -- video memory data ready |
v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address |
v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data |
|
blank: in std_logic; -- video sync generator blank output |
h_tc: in std_logic; -- horizontal sync pulse. Must be 1 clock wide! |
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0) |
); |
end mem_reader; |
|
architecture mem_reader of mem_reader is |
component fifo |
generic (fifo_width : positive; |
used_width : positive; |
fifo_depth : positive |
); |
port (d_in : in std_logic_vector(fifo_width-1 downto 0); |
clk : in std_logic; |
wr : in std_logic; |
rd : in std_logic; |
a_clr : in std_logic := '0'; |
s_clr : in std_logic := '0'; |
d_out : out std_logic_vector(fifo_width-1 downto 0); |
used : out std_logic_vector(used_width-1 downto 0); |
full : out std_logic; |
empty : out std_logic |
); |
end component; |
|
signal fifo_rd: std_logic; |
signal fifo_out: std_logic_vector(v_mem_width-1 downto 0); |
|
signal video_fifo_out: std_logic_vector(v_mem_width-1 downto 0); |
signal video_fifo_usedw: std_logic_vector(7 downto 0); |
signal video_fifo_rd: std_logic; |
signal video_fifo_full: std_logic; |
signal video_fifo_empty: std_logic; |
|
signal ds_fifo_out: std_logic_vector(v_mem_width-1 downto 0); |
-- signal ds_fifo_usedw: std_logic_vector(7 downto 0); |
signal ds_fifo_rd: std_logic; |
signal ds_fifo_clr: std_logic; |
-- signal ds_fifo_full: std_logic; |
-- signal ds_fifo_empty: std_logic; |
|
signal i_video_out: std_logic_vector(7 downto 0); |
signal ds_mode: std_logic; |
|
subtype pixel_cntr_var is integer range 0 to 7; |
|
-- signal i_v_mem_rd: std_logic := '0'; |
|
begin |
-- memory decoupler FIFO |
pixel_fifo: fifo |
generic map ( |
fifo_width => v_mem_width, |
used_width => 8, |
fifo_depth => fifo_size |
) |
port map ( |
d_in => v_mem_data, |
clk => clk, |
wr => v_mem_rdy, |
rd => video_fifo_rd, |
-- a_clr => '0', |
a_clr => reset, |
s_clr => reset, |
full => video_fifo_full, |
d_out => video_fifo_out, |
used => video_fifo_usedw, |
empty => video_fifo_empty |
); |
|
-- dual-scan FIFO |
ds_pixel_fifo: fifo |
generic map ( |
fifo_width => v_mem_width, |
used_width => 8, |
fifo_depth => dual_scan_fifo_size |
) |
port map ( |
d_in => fifo_out, |
clk => clk, |
wr => fifo_rd, |
rd => ds_fifo_rd, |
-- a_clr => '0', |
a_clr => reset, |
s_clr => ds_fifo_clr, |
d_out => ds_fifo_out |
); |
|
-- Multiplexer for DS data handling |
fifo_mux: for i in v_mem_width-1 downto 0 generate |
begin |
fifo_out(i) <= (video_fifo_out(i) and not ds_mode) or (ds_fifo_out(i) and ds_mode); |
-- fifo_out(i) <= (video_fifo_out(i) and not ds_mode); |
end generate; |
--fifo_out <= (video_fifo_out and not ds_mode); |
ds_fifo_rd <= ('0' and not ds_mode) or (fifo_rd and ds_mode); |
video_fifo_rd <= (fifo_rd and not ds_mode) or ('0' and ds_mode); |
|
-- Counter handles DS |
ds_counter : process is |
variable cnt: std_logic_vector(1 downto 0); |
begin |
wait until clk'EVENT and clk = '1'; |
if (reset = '1') then |
cnt := (others => '0'); |
ds_fifo_clr <= '1'; |
ds_mode <= '0'; |
else |
if (clk_en = '1') then |
if (h_tc = '1') then |
if (is_zero(cnt)) then |
ds_mode <= '0'; |
ds_fifo_clr <= '1'; |
else |
ds_mode <= '1'; |
ds_fifo_clr <= '0'; |
end if; |
if (cnt = multi_scan) then |
cnt := (others => '0'); |
else |
cnt := add_one(cnt); |
end if; |
else |
ds_fifo_clr <= '0'; |
end if; |
else |
ds_fifo_clr <= '1'; |
ds_mode <= '0'; |
end if; |
end if; |
end process; |
|
-- Pixel data reader state machine |
pixel_cntr : process is |
variable pixel_cnt: std_logic_vector(v_addr_width-1 downto 0); |
begin |
wait until clk'EVENT and clk='1'; |
if (reset = '1') then |
pixel_cnt := v_mem_start; |
else |
-- A little cheet. It won't work with constant v_mem_rdy. |
if (v_mem_rdy = '1') then |
-- data is already written to the FIFO, all we need to do is to update the counter, |
-- and remove the request |
if (pixel_cnt = v_mem_end) then |
pixel_cnt := v_mem_start; |
else |
pixel_cnt := add_one(pixel_cnt); |
end if; |
end if; |
end if; |
v_mem_addr <= pixel_cnt; |
end process; |
v_mem_rd <= (not video_fifo_full) and (not reset); |
|
-- Pixel data output state machine. |
pixel_output: process is |
subtype pixel_cntr_var is integer range 0 to v_mem_width-1; |
|
variable pixel_cntr : pixel_cntr_var; |
variable shift_reg : std_logic_vector (v_mem_width-1 downto 0); |
type rst_states is (in_reset,read,normal); |
variable rst_state : rst_states := in_reset; |
begin |
wait until clk'EVENT and clk='1'; |
if (reset = '1') then |
fifo_rd <= '0'; |
i_video_out <= (others => '0'); |
shift_reg := (others => '0'); |
pixel_cntr := 0; |
rst_state := in_reset; |
else |
if (not (rst_state = normal)) then |
-- perform one read after reset otherwise the picture will be shifted rigth one pixel |
case (rst_state) is |
when in_reset => |
if (video_fifo_empty = '0') then |
fifo_rd <= '1'; |
rst_state := read; |
else |
fifo_rd <= '0'; |
end if; |
when read => |
pixel_cntr := 0; |
shift_reg := fifo_out; |
fifo_rd <= '0'; |
rst_state := normal; |
when others => |
end case; |
else |
if (pix_clk_en = '0') then |
fifo_rd <= '0'; -- clear any pending read requests |
else |
if (blank = '1') then |
fifo_rd <= '0'; -- clear any pending read requests |
i_video_out <= (others => '0'); -- disable output |
-- i_video_out <= (others => 'U'); -- disable output |
else |
case (bpp) is |
when "00" => |
-- shift next data to the output and optionally read the next data from the fifo |
i_video_out(0) <= shift_reg(v_mem_width-1); |
i_video_out(7 downto 1) <= (others => '0'); |
if (pixel_cntr = v_mem_width-1) then |
-- Read next data |
pixel_cntr := 0; |
shift_reg := fifo_out; |
fifo_rd <= '0'; |
elsif (pixel_cntr = v_mem_width-2) then |
-- Request next data from FIFO |
pixel_cntr := pixel_cntr + 1; |
fifo_rd <= '1'; |
shift_reg := sl(shift_reg,1); |
else |
-- Simple increment |
pixel_cntr := pixel_cntr + 1; |
fifo_rd <= '0'; |
shift_reg := sl(shift_reg,1); |
end if; |
when "01" => |
-- shift next data to the output and optionally read the next data from the fifo |
i_video_out(1 downto 0) <= shift_reg(v_mem_width-1 downto v_mem_width-2); |
i_video_out(7 downto 2) <= (others => '0'); |
if (pixel_cntr = v_mem_width/2-1) then |
-- Read next data |
pixel_cntr := 0; |
shift_reg := fifo_out; |
fifo_rd <= '0'; |
elsif (pixel_cntr = v_mem_width/2-2) then |
-- Request next data from FIFO |
pixel_cntr := pixel_cntr + 1; |
fifo_rd <= '1'; |
shift_reg := sl(shift_reg,2); |
else |
-- Simple increment |
pixel_cntr := pixel_cntr + 1; |
fifo_rd <= '0'; |
shift_reg := sl(shift_reg,2); |
end if; |
when "10" => |
-- shift next data to the output and optionally read the next data from the fifo |
i_video_out(3 downto 0) <= shift_reg(v_mem_width-1 downto v_mem_width-4); |
i_video_out(7 downto 4) <= (others => '0'); |
if (pixel_cntr = v_mem_width/4-1) then |
-- Read next data |
pixel_cntr := 0; |
shift_reg := fifo_out; |
fifo_rd <= '0'; |
elsif (pixel_cntr = v_mem_width/4-2) then |
-- Request next data from FIFO |
pixel_cntr := pixel_cntr + 1; |
fifo_rd <= '1'; |
shift_reg := sl(shift_reg,4); |
else |
-- Simple increment |
pixel_cntr := pixel_cntr + 1; |
fifo_rd <= '0'; |
shift_reg := sl(shift_reg,4); |
end if; |
when "11" => |
if (v_mem_width = 8) then |
-- 8 bit memory with 8 bit output: every clock reads a byte from the fifo. |
fifo_rd <= '1'; |
i_video_out(7 downto 0) <= fifo_out; |
else |
-- shift next data to the output and optionally read the next data from the fifo |
i_video_out(7 downto 0) <= shift_reg(v_mem_width-1 downto v_mem_width-8); |
if (pixel_cntr = v_mem_width/8-1) then |
-- Read next data |
pixel_cntr := 0; |
shift_reg := fifo_out; |
fifo_rd <= '0'; |
elsif (pixel_cntr = v_mem_width/8-2) then |
-- Request next data from FIFO |
pixel_cntr := pixel_cntr + 1; |
fifo_rd <= '1'; |
shift_reg := sl(shift_reg,8); |
else |
-- Simple increment |
pixel_cntr := pixel_cntr + 1; |
fifo_rd <= '0'; |
shift_reg := sl(shift_reg,8); |
end if; |
end if; |
when others => -- Unsupported setting. Do nothing |
i_video_out(7 downto 0) <= (others => '0'); |
fifo_rd <= '0'; |
pixel_cntr := 0; |
end case; |
end if; |
end if; |
end if; |
end if; |
end process; |
|
video_out <= i_video_out; |
|
-- Simple logic generates the high_prior output |
priority: process is |
begin |
wait on video_fifo_usedw,fifo_treshold,video_fifo_full; |
if (video_fifo_usedw < fifo_treshold and video_fifo_full = '0') then |
high_prior <= '1'; |
else |
high_prior <= '0'; |
end if; |
end process; |
end mem_reader; |
/wb_vga/trunk/vga_chip.vhd
0,0 → 1,419
-- |
-- File: vga_chip.vhd |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
package constants is |
constant v_dat_width: positive := 16; |
constant v_adr_width : positive := 20; |
constant cpu_dat_width: positive := 32; |
constant cpu_adr_width: positive := 19; |
constant reg_adr_width: positive := 5; |
constant fifo_size: positive := 256; |
-- constant addr_diff: integer := log2(cpu_dat_width/v_dat_width); |
end constants; |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library wb_vga; |
use wb_vga.all; |
use wb_vga.constants.all; |
|
library wb_tk; |
use wb_tk.all; |
use wb_tk.technology.all; |
|
|
-- same as VGA_CORE but without generics. Suited for post-layout simulation. |
entity vga_chip is |
port ( |
clk_i: in std_logic; |
clk_en: in std_logic := '1'; |
rstn: in std_logic := '1'; |
|
-- CPU bus interface |
data: inout std_logic_vector (cpu_dat_width-1 downto 0) := (others => 'Z'); |
addr: in std_logic_vector (cpu_adr_width-1 downto 0) := (others => 'U'); |
rdn: in std_logic := '1'; |
wrn: in std_logic := '1'; |
vmem_cen: in std_logic := '1'; |
reg_cen: in std_logic := '1'; |
byen: in std_logic_vector ((cpu_dat_width/8)-1 downto 0); |
waitn: out std_logic; |
|
-- video memory SRAM interface |
s_data : inout std_logic_vector(v_dat_width-1 downto 0); |
s_addr : out std_logic_vector(v_adr_width-1 downto 0); |
s_oen : out std_logic; |
s_wrhn : out std_logic; |
s_wrln : out std_logic; |
s_cen : out std_logic; |
|
-- sync blank and video signal outputs |
h_sync: out std_logic; |
h_blank: out std_logic; |
v_sync: out std_logic; |
v_blank: out std_logic; |
h_tc: out std_logic; |
v_tc: out std_logic; |
blank: out std_logic; |
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0) |
); |
end vga_chip; |
|
architecture vga_chip of vga_chip is |
component wb_async_slave |
generic ( |
width: positive := 16; |
addr_width: positive := 20 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- interface for wait-state generator state-machine |
wait_state: in std_logic_vector (3 downto 0); |
|
-- interface to wishbone master device |
adr_i: in std_logic_vector (addr_width-1 downto 0); |
sel_i: in std_logic_vector ((addr_width/8)-1 downto 0); |
dat_i: in std_logic_vector (width-1 downto 0); |
dat_o: out std_logic_vector (width-1 downto 0); |
dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-'); |
we_i: in std_logic; |
stb_i: in std_logic; |
ack_o: out std_logic := '0'; |
ack_oi: in std_logic := '-'; |
|
-- interface to async slave |
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z'); |
a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U'); |
a_rdn: out std_logic := '1'; |
a_wrn: out std_logic := '1'; |
a_cen: out std_logic := '1'; |
-- byte-enable signals |
a_byen: out std_logic_vector ((width/8)-1 downto 0) |
); |
end component; |
|
component wb_async_master |
generic ( |
width: positive := 16; |
addr_width: positive := 20 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- interface to wb slave devices |
s_adr_o: out std_logic_vector (addr_width-1 downto 0); |
s_sel_o: out std_logic_vector ((width/8)-1 downto 0); |
s_dat_i: in std_logic_vector (width-1 downto 0); |
s_dat_o: out std_logic_vector (width-1 downto 0); |
s_cyc_o: out std_logic; |
s_ack_i: in std_logic; |
s_err_i: in std_logic := '-'; |
s_rty_i: in std_logic := '-'; |
s_we_o: out std_logic; |
s_stb_o: out std_logic; |
|
-- interface to asyncron master device |
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z'); |
a_addr: in std_logic_vector (addr_width-1 downto 0) := (others => 'U'); |
a_rdn: in std_logic := '1'; |
a_wrn: in std_logic := '1'; |
a_cen: in std_logic := '1'; |
a_byen: in std_logic_vector ((width/8)-1 downto 0); |
a_waitn: out std_logic |
); |
end component; |
|
component vga_core |
generic ( |
v_dat_width: positive := 16; |
v_adr_width : positive := 20; |
cpu_dat_width: positive := 16; |
cpu_adr_width: positive := 20; |
reg_adr_width: positive := 20; |
fifo_size: positive := 256 |
); |
port ( |
clk_i: in std_logic; |
clk_en: in std_logic := '1'; |
rst_i: in std_logic := '0'; |
|
-- CPU memory bus interface |
vmem_cyc_i: in std_logic; |
vmem_we_i: in std_logic; |
vmem_stb_i: in std_logic; -- selects video memory |
vmem_ack_o: out std_logic; |
vmem_ack_oi: in std_logic; |
vmem_adr_i: in std_logic_vector (cpu_adr_width-1 downto 0); |
vmem_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
vmem_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
vmem_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0); |
vmem_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
|
-- CPU register bus interface |
reg_cyc_i: in std_logic; |
reg_we_i: in std_logic; |
reg_stb_i: in std_logic; -- selects configuration registers |
reg_ack_o: out std_logic; |
reg_ack_oi: in std_logic; |
reg_adr_i: in std_logic_vector (reg_adr_width-1 downto 0); |
reg_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
reg_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
reg_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0); |
reg_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
|
-- video memory interface |
v_adr_o: out std_logic_vector (v_adr_width-1 downto 0); |
v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0); |
v_dat_i: in std_logic_vector (v_dat_width-1 downto 0); |
v_dat_o: out std_logic_vector (v_dat_width-1 downto 0); |
v_cyc_o: out std_logic; |
v_ack_i: in std_logic; |
v_we_o: out std_logic; |
v_stb_o: out std_logic; |
|
-- sync blank and video signal outputs |
h_sync: out std_logic; |
h_blank: out std_logic; |
v_sync: out std_logic; |
v_blank: out std_logic; |
h_tc: out std_logic; |
v_tc: out std_logic; |
blank: out std_logic; |
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0) |
); |
end component; |
|
component wb_out_reg |
generic ( |
width : positive := 8; |
bus_width: positive := 8; |
offset: integer := 0 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic; |
rst_val: std_logic_vector(width-1 downto 0) := (others => '0'); |
|
cyc_i: in std_logic := '1'; |
stb_i: in std_logic; |
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1'); |
we_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0'); |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
q: out std_logic_vector (width-1 downto 0) |
); |
end component; |
|
signal reg_ack_o: std_logic; |
signal reg_dat_o: std_logic_vector(cpu_dat_width-1 downto 0); |
|
signal reg_stb: std_logic; |
signal ws_stb: std_logic; |
signal wait_state: std_logic_vector(3 downto 0); |
|
signal v_adr_o: std_logic_vector (v_adr_width-1 downto 0); |
signal v_sel_o: std_logic_vector ((v_dat_width/8)-1 downto 0); |
signal v_dat_i: std_logic_vector (v_dat_width-1 downto 0); |
signal v_dat_o: std_logic_vector (v_dat_width-1 downto 0); |
signal v_cyc_o: std_logic; |
signal v_ack_i: std_logic; |
signal v_we_o: std_logic; |
signal v_stb_o: std_logic; |
|
signal s_byen : std_logic_vector((v_dat_width/8)-1 downto 0); |
|
signal ws_dat_o: std_logic_vector(cpu_dat_width-1 downto 0); |
signal ws_ack_o: std_logic; |
|
signal s_wrn: std_logic; |
|
|
signal dat_i: std_logic_vector (cpu_dat_width-1 downto 0); |
signal dat_oi: std_logic_vector (cpu_dat_width-1 downto 0); |
signal dat_o: std_logic_vector (cpu_dat_width-1 downto 0); |
signal cyc_i: std_logic; |
signal ack_o: std_logic; |
signal ack_oi: std_logic; |
signal we_i: std_logic; |
signal vmem_stb_i: std_logic; |
signal reg_stb_i: std_logic; |
signal adr_i: std_logic_vector (cpu_adr_width-1 downto 0); |
signal sel_i: std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
|
signal cen: std_logic; |
signal stb: std_logic; |
|
signal rst_i: std_logic := '0'; |
|
constant vga_reg_size: integer := size2bits((32*8+cpu_dat_width-1)/cpu_dat_width); |
begin |
rst_i <= not rstn; |
|
ws_reg: wb_out_reg |
generic map( width => 4, bus_width => cpu_dat_width , offset => 0 ) |
port map( |
stb_i => ws_stb, |
q => wait_state, |
rst_val => "1111", |
dat_oi => dat_oi, |
dat_o => ws_dat_o, |
ack_oi => ack_oi, |
ack_o => ws_ack_o, |
adr_i => adr_i(0 downto 0), -- range should be calculated !!! |
sel_i => sel_i, cyc_i => cyc_i, we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i ); |
|
core : vga_core |
generic map ( |
v_dat_width => v_dat_width, |
v_adr_width => v_adr_width, |
cpu_dat_width => cpu_dat_width, |
cpu_adr_width => cpu_adr_width, |
reg_adr_width => reg_adr_width, |
fifo_size => fifo_size |
) |
port map ( |
clk_i => clk_i, |
clk_en => clk_en, |
rst_i => rst_i, |
|
-- CPU bus interface |
vmem_cyc_i => cyc_i, |
vmem_we_i => we_i, |
vmem_stb_i => vmem_stb_i, |
vmem_ack_o => ack_o, |
vmem_ack_oi => reg_ack_o, |
vmem_adr_i => adr_i, |
vmem_sel_i => sel_i, |
vmem_dat_i => dat_i, |
vmem_dat_oi => reg_dat_o, |
vmem_dat_o => dat_o, |
|
-- CPU register bus interface |
reg_cyc_i => cyc_i, |
reg_we_i => we_i, |
reg_stb_i => reg_stb_i, |
reg_ack_o => reg_ack_o, |
reg_ack_oi => ack_oi, |
reg_adr_i => adr_i(reg_adr_width-1 downto 0), |
reg_sel_i => sel_i, |
reg_dat_i => dat_i, |
reg_dat_oi => dat_oi, |
reg_dat_o => reg_dat_o, |
|
|
-- video memory interface |
v_adr_o => v_adr_o, |
v_sel_o => v_sel_o, |
v_dat_i => v_dat_i, |
v_dat_o => v_dat_o, |
v_cyc_o => v_cyc_o, |
v_ack_i => v_ack_i, |
v_we_o => v_we_o, |
v_stb_o => v_stb_o, |
|
h_sync => h_sync, |
h_blank => h_blank, |
v_sync => v_sync, |
v_blank => v_blank, |
h_tc => h_tc, |
v_tc => v_tc, |
blank => blank, |
video_out => video_out |
); |
|
mem_driver: wb_async_slave |
generic map (width => v_dat_width, addr_width => v_adr_width) |
port map ( |
clk_i => clk_i, |
rst_i => rst_i, |
|
wait_state => wait_state, |
|
adr_i => v_adr_o, |
sel_i => v_sel_o, |
dat_o => v_dat_i, |
dat_i => v_dat_o, |
-- dat_oi => (others => '0'), |
we_i => v_we_o, |
stb_i => v_stb_o, |
ack_o => v_ack_i, |
ack_oi => '0', |
|
a_data => s_data, |
a_addr => s_addr, |
a_rdn => s_oen, |
a_wrn => s_wrn, |
a_cen => s_cen, |
a_byen => s_byen |
); |
|
s_wrln <= s_wrn or s_byen(0); |
s_wrhn <= s_wrn or s_byen(1); |
|
master: wb_async_master |
generic map ( |
width => cpu_dat_width, |
addr_width => cpu_adr_width |
) |
port map ( |
clk_i => clk_i, |
rst_i => rst_i, |
|
-- interface to wb slave devices |
s_adr_o => adr_i, |
s_sel_o => sel_i, |
s_dat_i => dat_o, |
s_dat_o => dat_i, |
s_cyc_o => cyc_i, |
s_ack_i => ack_o, |
s_err_i => '0', |
s_rty_i => '0', |
s_we_o => we_i, |
s_stb_o => stb, |
|
-- interface to asyncron master device |
a_data => data, |
a_addr => addr, |
a_rdn => rdn, |
a_wrn => wrn, |
a_cen => cen, |
a_byen => byen, |
a_waitn => waitn |
); |
|
cen <= vmem_cen and reg_cen; |
vmem_stb_i <= stb and not vmem_cen; |
reg_stb_i <= stb and not reg_cen; |
|
addr_decoder: process is |
begin |
wait on reg_stb_i, adr_i; |
|
reg_stb <= '0'; |
ws_stb <= '0'; |
|
if (reg_stb_i = '1') then |
case (adr_i(vga_reg_size)) is |
when '0' => reg_stb <= '1'; |
when '1' => ws_stb <= '1'; |
when others => |
end case; |
end if; |
end process; |
|
end vga_chip; |
/wb_vga/trunk/compile.sh
0,0 → 1,76
#!/bin/bash |
# |
# Script to compile sources to a library using Active HDL |
# (c) Copyright Andras Tantos <tantos@opencores.org> 2001/04/25 |
# This code is distributed under the terms and conditions of the GNU General Public Lince. |
# |
# USAGE: |
# |
# Set APATH to the installation directory of ActiveHDL and |
# LIB to whatever name your library has |
# RESULT_PATH to where generated files you wish to be put |
# Also make sure that you upadted the Library.cfg file to contain |
# the specified library name. |
# After the common part, list all files you wish to include in your library |
# with 'compile_file' preciding the file name. |
# |
# NOTES: |
# |
# This script depends on the following executables: |
# bash |
# cat |
# rm |
# mv |
# mkdir |
# echo |
# test |
# they are available under all UNIX-es and can be installed for windows |
# and DOS too. The windows version of these files can be obtained from |
# GNU Cygnus distribution (http://sources.redhat.com/cygwin) |
# The minimal package of these utilities are also available from |
# OpenCores web-site. |
|
APATH=C:/CAED/ActiveHDL.36/ |
LIB=wb_vga |
RESULT_PATH=ahdl |
|
# ___________Common part of the script____________ |
|
LIB_FILE=$RESULT_PATH/$LIB.lib |
CMP_FILE=$RESULT_PATH/0.mgf |
CMP=$APATH/bin/acombat.exe |
CMP_FLAGS="-avhdl $APATH -lib $LIB -93" |
|
compile_file() { |
LOG_FILE=$1 |
LOG_FILE=$RESULT_PATH/${LOG_FILE/.vhd/.rlt} |
ERR_FILE=${LOG_FILE/.rtl/.err} |
rm -f $LOG_FILE |
rm -f $ERR_FILE |
$CMP $CMP_FLAGS -log $LOG_FILE $1 || { |
mv $LOG_FILE $ERR_FILE |
cat $ERR_FILE |
exit 1 |
} |
cat $LOG_FILE |
} |
|
if test ! -d $RESULT_PATH; then |
mkdir $RESULT_PATH |
fi |
rm -f $RESULT_PATH/* |
if test ! -f $LIB_FILE; then |
echo > $LIB_FILE |
fi |
# ___________End of common part of the script____________ |
|
compile_file wb_io_reg.vhd |
compile_file mem_reader.vhd |
compile_file sync_gen.vhd |
compile_file hv_sync.vhd |
compile_file video_engine.vhd |
compile_file accel.vhd |
compile_file palette.vhd |
compile_file vga_core.vhd |
compile_file vga_core_v2.vhd |
compile_file vga_chip.vhd |
/wb_vga/trunk/vga_core.vhd
0,0 → 1,481
-- |
-- File: vga_core.vhd |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library wb_tk; |
use wb_tk.all; |
use wb_tk.technology.all; |
|
library wb_vga; |
use wb_vga.all; |
|
entity vga_core is |
generic ( |
v_dat_width: positive := 16; |
v_adr_width : positive := 20; |
cpu_dat_width: positive := 16; |
cpu_adr_width: positive := 20; |
reg_adr_width: positive := 20; |
fifo_size: positive := 256 |
); |
port ( |
clk_i: in std_logic; |
clk_en: in std_logic := '1'; |
rst_i: in std_logic := '0'; |
|
-- CPU memory bus interface |
vmem_cyc_i: in std_logic; |
vmem_we_i: in std_logic; |
vmem_stb_i: in std_logic; -- selects video memory |
vmem_ack_o: out std_logic; |
vmem_ack_oi: in std_logic; |
vmem_adr_i: in std_logic_vector (cpu_adr_width-1 downto 0); |
vmem_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
vmem_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
vmem_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0); |
vmem_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
|
-- CPU register bus interface |
reg_cyc_i: in std_logic; |
reg_we_i: in std_logic; |
reg_stb_i: in std_logic; -- selects configuration registers |
reg_ack_o: out std_logic; |
reg_ack_oi: in std_logic; |
reg_adr_i: in std_logic_vector (reg_adr_width-1 downto 0); |
reg_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
reg_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
reg_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0); |
reg_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
|
-- video memory interface |
v_adr_o: out std_logic_vector (v_adr_width-1 downto 0); |
v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0); |
v_dat_i: in std_logic_vector (v_dat_width-1 downto 0); |
v_dat_o: out std_logic_vector (v_dat_width-1 downto 0); |
v_cyc_o: out std_logic; |
v_ack_i: in std_logic; |
v_we_o: out std_logic; |
v_stb_o: out std_logic; |
|
-- sync blank and video signal outputs |
h_sync: out std_logic; |
h_blank: out std_logic; |
v_sync: out std_logic; |
v_blank: out std_logic; |
h_tc: out std_logic; |
v_tc: out std_logic; |
blank: out std_logic; |
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0) |
); |
end vga_core; |
|
architecture vga_core of vga_core is |
component video_engine |
generic ( |
v_mem_width: positive := 16; |
v_addr_width: positive:= 20; |
fifo_size: positive := 256; |
dual_scan_fifo_size: positive := 256 |
); |
port ( |
clk: in std_logic; |
clk_en: in std_logic := '1'; |
reset: in std_logic := '0'; |
|
v_mem_end: in std_logic_vector(v_addr_width-1 downto 0); -- video memory end address in words |
v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words |
fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold |
bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8 |
multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans |
|
hbs: in std_logic_vector(7 downto 0); |
hss: in std_logic_vector(7 downto 0); |
hse: in std_logic_vector(7 downto 0); |
htotal: in std_logic_vector(7 downto 0); |
vbs: in std_logic_vector(7 downto 0); |
vss: in std_logic_vector(7 downto 0); |
vse: in std_logic_vector(7 downto 0); |
vtotal: in std_logic_vector(7 downto 0); |
|
pps: in std_logic_vector(7 downto 0); |
|
high_prior: out std_logic; -- signals to the memory arbitrer to give high |
-- priority to the video engine |
v_mem_rd: out std_logic; -- video memory read request |
v_mem_rdy: in std_logic; -- video memory data ready |
v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address |
v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data |
|
h_sync: out std_logic; |
h_blank: out std_logic; |
v_sync: out std_logic; |
v_blank: out std_logic; |
h_tc: out std_logic; |
v_tc: out std_logic; |
blank: out std_logic; |
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0) |
); |
end component video_engine; |
|
component wb_arbiter |
port ( |
-- clk: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- interface to master device a |
a_we_i: in std_logic; |
a_stb_i: in std_logic; |
a_cyc_i: in std_logic; |
a_ack_o: out std_logic; |
a_ack_oi: in std_logic := '-'; |
a_err_o: out std_logic; |
a_err_oi: in std_logic := '-'; |
a_rty_o: out std_logic; |
a_rty_oi: in std_logic := '-'; |
|
-- interface to master device b |
b_we_i: in std_logic; |
b_stb_i: in std_logic; |
b_cyc_i: in std_logic; |
b_ack_o: out std_logic; |
b_ack_oi: in std_logic := '-'; |
b_err_o: out std_logic; |
b_err_oi: in std_logic := '-'; |
b_rty_o: out std_logic; |
b_rty_oi: in std_logic := '-'; |
|
-- interface to shared devices |
s_we_o: out std_logic; |
s_stb_o: out std_logic; |
s_cyc_o: out std_logic; |
s_ack_i: in std_logic; |
s_err_i: in std_logic := '-'; |
s_rty_i: in std_logic := '-'; |
|
mux_signal: out std_logic; -- 0: select A signals, 1: select B signals |
|
-- misc control lines |
priority: in std_logic -- 0: A have priority over B, 1: B have priority over A |
); |
end component; |
|
component wb_out_reg |
generic ( |
width : positive := 8; |
bus_width: positive := 8; |
offset: integer := 0 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic; |
rst_val: std_logic_vector(width-1 downto 0) := (others => '0'); |
|
cyc_i: in std_logic := '1'; |
stb_i: in std_logic; |
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1'); |
we_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0'); |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
q: out std_logic_vector (width-1 downto 0) |
); |
end component; |
|
component wb_bus_resize |
generic ( |
m_bus_width: positive; |
m_addr_width: positive; |
s_bus_width: positive; |
s_addr_width: positive; |
little_endien: boolean := true -- if set to false, big endien |
); |
port ( |
-- clk_i: in std_logic; |
-- rst_i: in std_logic := '0'; |
|
-- Master bus interface |
m_adr_i: in std_logic_vector (m_addr_width-1 downto 0); |
m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1'); |
m_dat_i: in std_logic_vector (m_bus_width-1 downto 0); |
m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-'); |
m_dat_o: out std_logic_vector (m_bus_width-1 downto 0); |
m_cyc_i: in std_logic; |
m_ack_o: out std_logic; |
m_ack_oi: in std_logic := '-'; |
m_err_o: out std_logic; |
m_err_oi: in std_logic := '-'; |
m_rty_o: out std_logic; |
m_rty_oi: in std_logic := '-'; |
m_we_i: in std_logic; |
m_stb_i: in std_logic; |
|
-- Slave bus interface |
s_adr_o: out std_logic_vector (s_addr_width-1 downto 0); |
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0); |
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0); |
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0); |
s_cyc_o: out std_logic; |
s_ack_i: in std_logic; |
s_err_i: in std_logic := '-'; |
s_rty_i: in std_logic := '-'; |
s_we_o: out std_logic; |
s_stb_o: out std_logic |
); |
end component; |
|
signal v_mem_start: std_logic_vector(v_adr_width-1 downto 0); |
signal v_mem_end: std_logic_vector(v_adr_width-1 downto 0); |
|
signal reg_bank: std_logic_vector((8*12)-1 downto 0); |
|
alias fifo_treshold: std_logic_vector(7 downto 0) is reg_bank( 7 downto 0); |
alias bpp: std_logic_vector(1 downto 0) is reg_bank( 9 downto 8); |
alias multi_scan: std_logic_vector(1 downto 0) is reg_bank(13 downto 12); |
alias hbs: std_logic_vector(7 downto 0) is reg_bank(23 downto 16); |
alias hss: std_logic_vector(7 downto 0) is reg_bank(31 downto 24); |
alias hse: std_logic_vector(7 downto 0) is reg_bank(39 downto 32); |
alias htotal: std_logic_vector(7 downto 0) is reg_bank(47 downto 40); |
alias vbs: std_logic_vector(7 downto 0) is reg_bank(55 downto 48); |
alias vss: std_logic_vector(7 downto 0) is reg_bank(63 downto 56); |
alias vse: std_logic_vector(7 downto 0) is reg_bank(71 downto 64); |
alias vtotal: std_logic_vector(7 downto 0) is reg_bank(79 downto 72); |
alias pps: std_logic_vector(7 downto 0) is reg_bank(87 downto 80); |
alias sync_pol: std_logic_vector (3 downto 0) is reg_bank(91 downto 88); |
alias reset_core: std_logic_vector(0 downto 0) is reg_bank(95 downto 95); |
|
signal v_mem_start_stb: std_logic; -- selects total register |
signal v_mem_end_stb: std_logic; -- selects offset register |
signal reg_bank_stb: std_logic; -- selects all other registers (in a single bank) |
|
signal reg_bank_do: std_logic_vector(cpu_dat_width-1 downto 0); |
signal v_mem_start_do: std_logic_vector(cpu_dat_width-1 downto 0); |
|
signal reg_bank_ack: std_logic; |
signal v_mem_start_ack: std_logic; |
|
signal a_adr_o : std_logic_vector((v_adr_width-1) downto 0); |
signal a_sel_o : std_logic_vector((v_dat_width/8)-1 downto 0); |
signal a_dat_o : std_logic_vector((v_dat_width-1) downto 0); |
signal a_dat_i : std_logic_vector((v_dat_width-1) downto 0); |
signal a_we_o : std_logic; |
signal a_stb_o : std_logic; |
signal a_cyc_o : std_logic; |
signal a_ack_i : std_logic; |
|
signal b_adr_o : std_logic_vector((v_adr_width-1) downto 0); |
signal b_sel_o : std_logic_vector((v_dat_width/8)-1 downto 0); |
-- signal b_dat_o : std_logic_vector((v_dat_width-1) downto 0); |
signal b_dat_i : std_logic_vector((v_dat_width-1) downto 0); |
signal b_stb_o : std_logic; |
-- signal b_we_o : std_logic; |
-- signal b_cyc_o : std_logic; |
signal b_ack_i : std_logic; |
|
signal mux_signal: std_logic; |
|
signal high_prior: std_logic; |
|
signal reset_engine: std_logic; |
|
signal i_h_sync: std_logic; |
signal i_h_blank: std_logic; |
signal i_v_sync: std_logic; |
signal i_v_blank: std_logic; |
|
signal s_wrn : std_logic; |
|
constant v_adr_zero : std_logic_vector(v_adr_width-1 downto 0) := (others => '0'); |
constant reg_bank_rst_val: std_logic_vector(reg_bank'Range) := (others => '0'); |
constant reg_bank_size: integer := size2bits((reg_bank'HIGH+cpu_dat_width)/cpu_dat_width); |
constant tot_ofs_size: integer := size2bits((v_adr_width+cpu_dat_width-1)/cpu_dat_width); |
begin |
-- map all registers: |
-- adr_i: in std_logic_vector (max(log2((width+offset+bus_width-1)/bus_width)-1,0) downto 0) := (others => '0'); |
|
reg_bank_reg: wb_out_reg |
generic map( width => reg_bank'HIGH+1, bus_width => cpu_dat_width , offset => 0 ) |
port map( |
stb_i => reg_bank_stb, |
q => reg_bank, |
rst_val => reg_bank_rst_val, |
dat_oi => reg_dat_oi, |
dat_o => reg_bank_do, |
ack_oi => reg_ack_oi, |
ack_o => reg_bank_ack, |
adr_i => reg_adr_i(reg_bank_size-1 downto 0), |
sel_i => reg_sel_i, cyc_i => reg_cyc_i, we_i => reg_we_i, clk_i => clk_i, rst_i => rst_i, dat_i => reg_dat_i ); |
v_mem_start_reg: wb_out_reg |
generic map( width => v_adr_width, bus_width => cpu_dat_width , offset => 0 ) |
port map( |
stb_i => v_mem_start_stb, |
q => v_mem_start, |
rst_val => v_adr_zero, |
dat_oi => reg_bank_do, |
dat_o => v_mem_start_do, |
ack_oi => reg_bank_ack, |
ack_o => v_mem_start_ack, |
adr_i => reg_adr_i(tot_ofs_size-1 downto 0), |
sel_i => reg_sel_i, cyc_i => reg_cyc_i, we_i => reg_we_i, clk_i => clk_i, rst_i => rst_i, dat_i => reg_dat_i ); |
v_mem_end_reg: wb_out_reg |
generic map( width => v_adr_width, bus_width => cpu_dat_width , offset => 0 ) |
port map( |
stb_i => v_mem_end_stb, |
q => v_mem_end, |
rst_val => v_adr_zero, |
dat_oi => v_mem_start_do, |
dat_o => reg_dat_o, -- END OF THE CHAIN |
ack_oi => v_mem_start_ack, |
ack_o => reg_ack_o, -- END OF THE CHAIN |
adr_i => reg_adr_i(tot_ofs_size-1 downto 0), |
sel_i => reg_sel_i, cyc_i => reg_cyc_i, we_i => reg_we_i, clk_i => clk_i, rst_i => rst_i, dat_i => reg_dat_i ); |
|
reset_engine <= rst_i or not reset_core(0); |
|
v_e: video_engine |
generic map ( v_mem_width => v_dat_width, v_addr_width => v_adr_width, fifo_size => fifo_size, dual_scan_fifo_size => fifo_size ) |
port map ( |
clk => clk_i, |
clk_en => clk_en, |
reset => reset_engine, |
v_mem_start => v_mem_start, |
v_mem_end => v_mem_end, |
fifo_treshold => fifo_treshold, |
bpp => bpp, |
multi_scan => multi_scan, |
hbs => hbs, |
hss => hss, |
hse => hse, |
htotal => htotal, |
vbs => vbs, |
vss => vss, |
vse => vse, |
vtotal => vtotal, |
pps => pps, |
|
high_prior => high_prior, |
|
v_mem_rd => b_stb_o, |
v_mem_rdy => b_ack_i, |
v_mem_addr => b_adr_o, |
v_mem_data => b_dat_i, |
|
h_sync => i_h_sync, |
h_blank => i_h_blank, |
v_sync => i_v_sync, |
v_blank => i_v_blank, |
h_tc => h_tc, |
v_tc => v_tc, |
blank => blank, |
video_out => video_out |
); |
|
h_sync <= i_h_sync xor sync_pol(0); |
v_sync <= i_v_sync xor sync_pol(1); |
h_blank <= i_h_blank;-- xor sync_pol(2); |
v_blank <= i_v_blank;-- xor sync_pol(3); |
|
resize: wb_bus_resize |
generic map ( |
m_bus_width => cpu_dat_width, s_bus_width => v_dat_width, m_addr_width => cpu_adr_width, s_addr_width => v_adr_width, little_endien => true |
) |
port map ( |
m_adr_i => vmem_adr_i, |
m_cyc_i => vmem_cyc_i, |
m_sel_i => vmem_sel_i, |
m_dat_i => vmem_dat_i, |
m_dat_oi => vmem_dat_oi, |
m_dat_o => vmem_dat_o, |
m_ack_o => vmem_ack_o, |
m_ack_oi => vmem_ack_oi, -- Beginning of the chain |
m_we_i => vmem_we_i, |
m_stb_i => vmem_stb_i, |
|
s_adr_o => a_adr_o, |
s_sel_o => a_sel_o, |
s_dat_i => a_dat_i, |
s_dat_o => a_dat_o, |
s_cyc_o => a_cyc_o, |
s_ack_i => a_ack_i, |
s_we_o => a_we_o, |
s_stb_o => a_stb_o |
); |
|
|
arbiter: wb_arbiter |
port map ( |
rst_i => reset_engine, |
|
a_we_i => a_we_o, |
a_cyc_i => a_cyc_o, |
a_stb_i => a_stb_o, |
a_ack_o => a_ack_i, |
a_ack_oi => '-', |
|
b_we_i => '0', |
b_cyc_i => b_stb_o, |
b_stb_i => b_stb_o, |
b_ack_o => b_ack_i, |
b_ack_oi => '0', |
|
s_we_o => v_we_o, |
s_stb_o => v_stb_o, |
s_ack_i => v_ack_i, |
s_cyc_o => v_cyc_o, |
|
mux_signal => mux_signal, |
|
priority => high_prior |
); |
|
b_sel_o <= (others => '1'); |
|
bus_mux: process is |
begin |
wait on mux_signal, v_dat_i, a_adr_o, a_dat_o, b_adr_o, a_sel_o, b_sel_o; |
if (mux_signal = '0') then |
v_adr_o <= a_adr_o; |
v_sel_o <= a_sel_o; |
v_dat_o <= a_dat_o; |
a_dat_i <= v_dat_i; |
b_dat_i <= (others => '-'); |
else |
v_adr_o <= b_adr_o; |
v_sel_o <= b_sel_o; |
v_dat_o <= (others => '-'); |
b_dat_i <= v_dat_i; |
a_dat_i <= (others => '-'); |
end if; |
end process; |
|
addr_decoder: process is |
begin |
wait on reg_stb_i, reg_adr_i; |
|
v_mem_start_stb <= '0'; |
v_mem_end_stb <= '0'; |
reg_bank_stb <= '0'; |
|
if (reg_stb_i = '1') then |
case (reg_adr_i(reg_bank_size)) is |
when '0' => |
case (reg_adr_i(reg_bank_size-2)) is |
when '0' => v_mem_end_stb <= '1'; |
when '1' => v_mem_start_stb <= '1'; |
when others => |
end case; |
when '1' => reg_bank_stb <= '1'; |
when others => |
end case; |
end if; |
end process; |
end vga_core; |
|
/wb_vga/trunk/accel.vhd
0,0 → 1,240
-- |
-- Address generator and accelerator. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
|
|
-- Standard library. |
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.numeric_std.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
use wb_tk.all; |
|
library wb_vga; |
use wb_vga.all; |
|
entity accel is |
generic ( |
accel_size: positive := 9; |
video_addr_width: positive := 20; |
data_width: positive := 16 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- Slave interface to the CPU side |
we_i: in std_logic; |
cyc_i: in std_logic; |
cur_stb_i: in std_logic; |
ext_stb_i: in std_logic; |
acc_stb_i: in std_logic; |
mem_stb_i: in std_logic; |
|
sel_i: in std_logic_vector ((data_width/8)-1 downto 0) := (others => '1'); |
adr_i: in std_logic_vector(accel_size-1 downto 0); |
dat_i: in std_logic_vector(data_width-1 downto 0); |
dat_o: out std_logic_vector(data_width-1 downto 0); |
dat_oi: in std_logic_vector(data_width-1 downto 0); |
|
ack_o: out std_logic; |
ack_oi: in std_logic; |
|
-- Master interface to the video memory side. |
v_we_o: out std_logic; |
v_cyc_o: out std_logic; |
v_stb_o: out std_logic; |
|
v_adr_o: out std_logic_vector (video_addr_width-1 downto 0); |
v_sel_o: out std_logic_vector ((data_width/8)-1 downto 0); |
v_dat_o: out std_logic_vector (data_width-1 downto 0); |
v_dat_i: in std_logic_vector (data_width-1 downto 0); |
|
v_ack_i: in std_logic |
); |
end accel; |
|
architecture accel of accel is |
component wb_io_reg |
generic ( |
width : positive := video_addr_width; |
bus_width: positive := data_width; |
offset: integer := 0 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic; |
rst_val: std_logic_vector(width-1 downto 0) := (others => '0'); |
|
cyc_i: in std_logic := '1'; |
stb_i: in std_logic; |
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1'); |
we_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0'); |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
q: out std_logic_vector (width-1 downto 0); |
ext_d: in std_logic_vector (width-1 downto 0) := (others => '-'); |
ext_we: in std_logic := '0' |
); |
end component; |
|
component wb_ram |
generic ( |
data_width: positive := 8; |
addr_width: positive := 10 |
); |
port ( |
clk_i: in std_logic; |
adr_i: in std_logic_vector (addr_width-1 downto 0); |
dat_i: in std_logic_vector (data_width-1 downto 0); |
dat_oi: in std_logic_vector (data_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (data_width-1 downto 0); |
cyc_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
we_i: in std_logic; |
stb_i: in std_logic |
); |
end component; |
|
signal cursor: std_logic_vector(video_addr_width-1 downto 0); |
signal accel_ram_d_out: std_logic_vector(video_addr_width-1 downto 0); |
signal accel_ram_dat_i: std_logic_vector(video_addr_width-1 downto 0); |
signal accel_ram_stb: std_logic; |
signal accel_ram_ack: std_logic; |
signal accel_ram_we: std_logic; |
signal accel_ram_clk: std_logic; |
signal next_cur: std_logic_vector(video_addr_width-1 downto 0); |
signal cur_update: std_logic := '0'; |
signal mem_ack_o: std_logic := '1'; |
signal mem_dat_o: std_logic_vector(data_width-1 downto 0); |
signal cur_ack_o: std_logic := '1'; |
signal cur_dat_o: std_logic_vector(data_width-1 downto 0); |
signal ext_value: std_logic_vector(max(video_addr_width - data_width,1)-1 downto 0); |
signal ext_ext_we: std_logic; |
begin |
accel_ram_stb <= acc_stb_i or mem_stb_i; |
accel_ram_we <= we_i and acc_stb_i; |
accel_ram_clk <= clk_i; |
accel_ram_dat_i(min2(video_addr_width-1 |
,data_width-1) downto 0) <= |
dat_i(min2(video_addr_width,data_width) - 1 downto 0); |
high_accel_dat_gen: if (video_addr_width > data_width) generate |
accel_ram_dat_i(video_addr_width-1 downto data_width) <= ext_value; |
end generate; |
accel_ram: wb_ram |
generic map ( |
data_width => video_addr_width, |
addr_width => accel_size |
) |
port map ( |
clk_i => clk_i, |
cyc_i => cyc_i, |
stb_i => accel_ram_stb, |
we_i => accel_ram_we, |
adr_i => adr_i, |
dat_i => accel_ram_dat_i, |
dat_o => accel_ram_d_out, |
ack_o => accel_ram_ack |
); |
|
v_stb_o <= mem_stb_i; |
v_cyc_o <= mem_stb_i and cyc_i; |
v_adr_o <= cursor; |
v_we_o <= we_i; |
v_dat_o <= dat_i; |
|
next_cur <= cursor + accel_ram_d_out; |
|
ext_ext_we <= acc_stb_i and not we_i; |
ext_reg_gen: if (video_addr_width > data_width) generate |
ext_reg: wb_io_reg |
generic map ( |
width => video_addr_width - data_width, |
bus_width => data_width, |
offset => 0 |
) |
port map ( |
clk_i => clk_i, |
rst_i => rst_i, |
rst_val => (video_addr_width - data_width-1 downto 0 => '0'), |
|
cyc_i => cyc_i, |
stb_i => ext_stb_i, |
sel_i => sel_i, |
we_i => we_i, |
ack_o => ack_o, |
ack_oi => cur_ack_o, |
adr_i => adr_i(size2bits((video_addr_width-1)/data_width)-1 downto 0), |
dat_i => dat_i, |
dat_oi => cur_dat_o, |
dat_o => dat_o, |
q => ext_value, |
ext_d => accel_ram_d_out(video_addr_width-1 downto data_width), |
ext_we => ext_ext_we |
); |
end generate; |
ext_gen: if (video_addr_width <= data_width) generate |
dat_o <= cur_dat_o; |
ack_o <= cur_ack_o; |
ext_value(0) <= '0'; |
end generate; |
|
cur_reg: wb_io_reg |
generic map ( |
width => video_addr_width, |
bus_width => data_width, |
offset => 0 |
) |
port map ( |
clk_i => clk_i, |
rst_i => rst_i, |
rst_val => (video_addr_width-1 downto 0 => '0'), |
|
cyc_i => cyc_i, |
stb_i => cur_stb_i, |
sel_i => sel_i, |
we_i => we_i, |
ack_o => cur_ack_o, |
ack_oi => mem_ack_o, |
adr_i => adr_i(size2bits((video_addr_width+data_width-1)/data_width)-1 downto 0), |
dat_i => dat_i, |
dat_oi => mem_dat_o, |
dat_o => cur_dat_o, |
q => cursor, |
ext_d => next_cur, |
ext_we => cur_update |
); |
|
cur_update <= mem_stb_i and cyc_i and v_ack_i; |
|
v_sel_o <= sel_i; |
gen_dat_o: for i in dat_o'RANGE generate |
gen_dat_o1: if (i < video_addr_width) generate |
mem_dat_o(i) <= ( |
(cyc_i and ((accel_ram_d_out(i) and acc_stb_i) or (v_dat_i(i) and mem_stb_i))) or |
(dat_oi(i) and ((not (acc_stb_i or mem_stb_i or cur_stb_i)) or (not cyc_i))) |
); |
end generate; |
gen_dat_o2: if (i >= video_addr_width) generate |
mem_dat_o(i) <= ( |
(cyc_i and (('0' and acc_stb_i) or (v_dat_i(i) and mem_stb_i))) or |
(dat_oi(i) and ((not (acc_stb_i or mem_stb_i or cur_stb_i)) or (not cyc_i))) |
); |
end generate; |
end generate; |
mem_ack_o <= ( |
(cyc_i and ((accel_ram_ack and acc_stb_i) or (v_ack_i and mem_stb_i))) or |
(ack_oi and ((not (acc_stb_i or mem_stb_i or cur_stb_i)) or (not cyc_i))) |
); |
|
end accel; |
/wb_vga/trunk/video_engine.vhd
0,0 → 1,226
-- |
-- File: video_engine.vhd |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
|
entity video_engine is |
generic ( |
v_mem_width: positive := 16; |
v_addr_width: positive:= 20; |
fifo_size: positive := 256; |
dual_scan_fifo_size: positive := 256 |
); |
port ( |
clk: in std_logic; |
clk_en: in std_logic := '1'; |
reset: in std_logic := '0'; |
|
v_mem_end: in std_logic_vector(v_addr_width-1 downto 0); -- video memory end address in words |
v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words |
fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold |
bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8 |
multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans |
|
hbs: in std_logic_vector(7 downto 0); |
hss: in std_logic_vector(7 downto 0); |
hse: in std_logic_vector(7 downto 0); |
htotal: in std_logic_vector(7 downto 0); |
vbs: in std_logic_vector(7 downto 0); |
vss: in std_logic_vector(7 downto 0); |
vse: in std_logic_vector(7 downto 0); |
vtotal: in std_logic_vector(7 downto 0); |
|
pps: in std_logic_vector(7 downto 0); |
|
high_prior: out std_logic; -- signals to the memory arbitrer to give high |
-- priority to the video engine |
v_mem_rd: out std_logic; -- video memory read request |
v_mem_rdy: in std_logic; -- video memory data ready |
v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address |
v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data |
|
h_sync: out std_logic; |
h_blank: out std_logic; |
v_sync: out std_logic; |
v_blank: out std_logic; |
h_tc: out std_logic; |
v_tc: out std_logic; |
blank: out std_logic; |
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0) |
); |
end video_engine; |
|
architecture video_engine of video_engine is |
component hv_sync |
port ( |
clk: in std_logic; |
pix_clk_en: in std_logic := '1'; |
reset: in std_logic := '0'; |
|
hbs: in std_logic_vector(7 downto 0); |
hss: in std_logic_vector(7 downto 0); |
hse: in std_logic_vector(7 downto 0); |
htotal: in std_logic_vector(7 downto 0); |
vbs: in std_logic_vector(7 downto 0); |
vss: in std_logic_vector(7 downto 0); |
vse: in std_logic_vector(7 downto 0); |
vtotal: in std_logic_vector(7 downto 0); |
|
h_sync: out std_logic; |
h_blank: out std_logic; |
v_sync: out std_logic; |
v_blank: out std_logic; |
h_tc: out std_logic; |
v_tc: out std_logic; |
blank: out std_logic |
); |
end component; |
|
component mem_reader |
generic ( |
v_mem_width: positive := 16; |
v_addr_width: positive:= 20; |
fifo_size: positive := 256; |
dual_scan_fifo_size: positive := 256 |
); |
port ( |
clk: in std_logic; |
clk_en: in std_logic; |
pix_clk_en: in std_logic; |
reset: in std_logic := '0'; |
|
v_mem_end: in std_logic_vector(v_addr_width-1 downto 0); -- video memory end address in words |
v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words |
fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold |
bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8 |
multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans |
|
high_prior: out std_logic; -- signals to the memory arbitrer to give high |
-- priority to the video engine |
v_mem_rd: out std_logic; -- video memory read request |
v_mem_rdy: in std_logic; -- video memory data ready |
v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address |
v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data |
|
blank: in std_logic; -- video sync generator blank output |
h_tc: in std_logic; -- horizontal sync pulse. Must be 1 clock wide! |
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0) |
); |
end component; |
|
signal pix_clk_en: std_logic; |
|
signal i_h_sync: std_logic; |
signal i_h_blank: std_logic; |
signal i_v_sync: std_logic; |
signal i_v_blank: std_logic; |
signal i_h_tc: std_logic; |
signal i_v_tc: std_logic; |
signal i_blank: std_logic; |
|
begin |
pps_gen: process is |
variable cnt: std_logic_vector(3 downto 0); |
begin |
wait until clk'EVENT and clk = '1'; |
if (reset = '1') then |
cnt := (others => '0'); |
pix_clk_en <= '0'; |
else |
if (clk_en = '0') then |
pix_clk_en <= '0'; |
else |
if (cnt = pps(3 downto 0)) then |
cnt := (others => '0'); |
pix_clk_en <= '1'; |
else |
cnt := add_one(cnt); |
pix_clk_en <= '0'; |
end if; |
end if; |
end if; |
end process; |
|
mem_engine : mem_reader |
generic map ( |
v_mem_width => v_mem_width, |
v_addr_width => v_addr_width, |
fifo_size => fifo_size, |
dual_scan_fifo_size => dual_scan_fifo_size |
) |
port map ( |
clk => clk, |
clk_en => clk_en, |
pix_clk_en => pix_clk_en, |
reset => reset, |
v_mem_end => v_mem_end, |
v_mem_start => v_mem_start, |
fifo_treshold => fifo_treshold, |
bpp => bpp, |
multi_scan => multi_scan, |
high_prior => high_prior, |
v_mem_rd => v_mem_rd, |
v_mem_rdy => v_mem_rdy, |
v_mem_addr => v_mem_addr, |
v_mem_data => v_mem_data, |
blank => i_blank, |
h_tc => i_h_tc, |
video_out => video_out |
); |
|
sync_engine : hv_sync |
port map ( |
clk => clk, |
pix_clk_en => pix_clk_en, |
reset => reset, |
|
hbs => hbs, |
hss => hss, |
hse => hse, |
htotal => htotal, |
vbs => vbs, |
vss => vss, |
vse => vse, |
vtotal => vtotal, |
|
h_sync => i_h_sync, |
h_blank => i_h_blank, |
v_sync => i_v_sync, |
v_blank => i_v_blank, |
h_tc => i_h_tc, |
v_tc => i_v_tc, |
blank => i_blank |
); |
|
-- Delay all sync signals with one pixel. That's becouse of the syncron output of the mem_reader |
sync_delay: process is |
begin |
wait until (clk'EVENT and clk='1'); |
if (reset = '1') then |
h_sync <= '0'; |
h_blank <= '1'; |
v_sync <= '0'; |
v_blank <= '1'; |
blank <= '1'; |
elsif (pix_clk_en = '1') then |
h_sync <= i_h_sync; |
h_blank <= i_h_blank; |
v_sync <= i_v_sync; |
v_blank <= i_v_blank; |
blank <= i_blank; |
end if; |
end process; |
|
h_tc <= i_h_tc; |
v_tc <= i_v_tc; |
|
end video_engine; |
|
/wb_vga/trunk/vga_core_v2.vhd
0,0 → 1,386
-- |
-- File: vga_core_v2.vhd |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/04/26 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
-- vga_core_v2: A WB compatible monitor controller core with version2 features. |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library wb_vga; |
use wb_vga.all; |
|
library wb_tk; |
use wb_tk.all; |
use wb_tk.technology.all; |
|
entity vga_core_v2 is |
generic ( |
v_dat_width: positive := 16; |
v_adr_width : positive := 20; |
cpu_dat_width: positive := 16; |
cpu_adr_width: positive := 11; |
fifo_size: positive := 256; |
accel_size: positive := 9; |
v_pal_size: positive := 8; |
v_pal_width: positive := 16 |
); |
port ( |
clk_i: in std_logic; |
clk_en: in std_logic := '1'; |
rst_i: in std_logic := '0'; |
|
-- CPU bus interface |
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
cyc_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic; |
err_o: out std_logic; |
err_oi: in std_logic; |
we_i: in std_logic; |
accel_stb_i: in std_logic; |
pal_stb_i: in std_logic; |
reg_stb_i: in std_logic; |
adr_i: in std_logic_vector (cpu_adr_width-1 downto 0); |
sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
|
-- video memory interface |
v_adr_o: out std_logic_vector (v_adr_width-1 downto 0); |
v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0); |
v_dat_i: in std_logic_vector (v_dat_width-1 downto 0); |
v_dat_o: out std_logic_vector (v_dat_width-1 downto 0); |
v_cyc_o: out std_logic; |
v_ack_i: in std_logic; |
v_we_o: out std_logic; |
v_stb_o: out std_logic; |
|
-- sync blank and video signal outputs |
h_sync: out std_logic; |
h_blank: out std_logic; |
v_sync: out std_logic; |
v_blank: out std_logic; |
h_tc: out std_logic; |
v_tc: out std_logic; |
blank: out std_logic; |
video_out: out std_logic_vector (v_pal_size-1 downto 0); -- video output binary signal (unused bits are forced to 0) |
true_color_out: out std_logic_vector (v_pal_width-1 downto 0) -- true-color video output |
); |
end vga_core_v2; |
|
architecture vga_core_v2 of vga_core_v2 is |
component vga_core |
generic ( |
v_dat_width: positive := v_dat_width; |
v_adr_width : positive := v_adr_width; |
cpu_dat_width: positive := cpu_dat_width; |
cpu_adr_width: positive := v_adr_width-bus_resize2adr_bits(cpu_dat_width,v_dat_width); |
reg_adr_width: positive := cpu_adr_width; |
fifo_size: positive := fifo_size |
); |
port ( |
clk_i: in std_logic; |
clk_en: in std_logic := '1'; |
rst_i: in std_logic := '0'; |
|
-- CPU memory bus interface |
vmem_cyc_i: in std_logic; |
vmem_we_i: in std_logic; |
vmem_stb_i: in std_logic; -- selects video memory |
vmem_ack_o: out std_logic; |
vmem_ack_oi: in std_logic; |
vmem_adr_i: in std_logic_vector (cpu_adr_width-1 downto 0); |
vmem_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
vmem_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
vmem_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0); |
vmem_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
|
-- CPU register bus interface |
reg_cyc_i: in std_logic; |
reg_we_i: in std_logic; |
reg_stb_i: in std_logic; -- selects configuration registers |
reg_ack_o: out std_logic; |
reg_ack_oi: in std_logic; |
reg_adr_i: in std_logic_vector (reg_adr_width-1 downto 0); |
reg_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
reg_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
reg_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0); |
reg_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
|
-- video memory interface |
v_adr_o: out std_logic_vector (v_adr_width-1 downto 0); |
v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0); |
v_dat_i: in std_logic_vector (v_dat_width-1 downto 0); |
v_dat_o: out std_logic_vector (v_dat_width-1 downto 0); |
v_cyc_o: out std_logic; |
v_ack_i: in std_logic; |
v_we_o: out std_logic; |
v_stb_o: out std_logic; |
|
-- sync blank and video signal outputs |
h_sync: out std_logic; |
h_blank: out std_logic; |
v_sync: out std_logic; |
v_blank: out std_logic; |
h_tc: out std_logic; |
v_tc: out std_logic; |
blank: out std_logic; |
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0) |
); |
end component; |
|
component accel is |
generic ( |
accel_size: positive := accel_size; |
video_addr_width: positive := v_adr_width-bus_resize2adr_bits(cpu_dat_width,v_dat_width); |
data_width: positive := cpu_dat_width |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
|
-- Slave interface to the CPU side |
we_i: in std_logic; |
cyc_i: in std_logic; |
cur_stb_i: in std_logic; |
ext_stb_i: in std_logic; |
acc_stb_i: in std_logic; |
mem_stb_i: in std_logic; |
|
sel_i: in std_logic_vector ((data_width/8)-1 downto 0) := (others => '1'); |
adr_i: in std_logic_vector(accel_size-1 downto 0); |
dat_i: in std_logic_vector(data_width-1 downto 0); |
dat_o: out std_logic_vector(data_width-1 downto 0); |
dat_oi: in std_logic_vector(data_width-1 downto 0); |
|
ack_o: out std_logic; |
ack_oi: in std_logic; |
|
-- Master interface to the video memory side. |
v_we_o: out std_logic; |
v_cyc_o: out std_logic; |
v_stb_o: out std_logic; |
|
v_adr_o: out std_logic_vector (video_addr_width-1 downto 0); |
v_sel_o: out std_logic_vector ((data_width/8)-1 downto 0); |
v_dat_o: out std_logic_vector (data_width-1 downto 0); |
v_dat_i: in std_logic_vector (data_width-1 downto 0); |
|
v_ack_i: in std_logic |
); |
end component; |
|
component wb_pal_ram is |
generic ( |
cpu_dat_width: positive := cpu_dat_width; |
cpu_adr_width: positive := v_pal_size-bus_resize2adr_bits(cpu_dat_width,v_dat_width); |
v_dat_width: positive := v_pal_width; |
v_adr_width: positive := v_pal_size |
); |
port ( |
-- Wishbone interface to CPU (write-only support) |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
adr_i: in std_logic_vector (cpu_adr_width-1 downto 0); |
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
cyc_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
err_o: out std_logic; |
err_oi: in std_logic := '-'; |
we_i: in std_logic; |
stb_i: in std_logic; |
-- Interface to the video output |
blank: in std_logic; |
v_dat_i: in std_logic_vector(v_adr_width-1 downto 0); |
v_dat_o: out std_logic_vector(v_dat_width-1 downto 0) |
); |
end component; |
|
-- register select signals |
signal vga_reg_stb: std_logic; |
signal cur_stb: std_logic; |
signal ext_stb: std_logic; |
-- accelerator select signals |
signal acc_stb: std_logic; |
signal mem_stb: std_logic; |
|
signal vga_dat_o: std_logic_vector(cpu_dat_width-1 downto 0); |
signal vga_ack_o: std_logic; |
|
signal vreg_dat_o: std_logic_vector(cpu_dat_width-1 downto 0); |
signal vreg_ack_o: std_logic; |
signal accel_dat_o: std_logic_vector(cpu_dat_width-1 downto 0); |
signal accel_ack_o: std_logic; |
signal pal_dat_o: std_logic_vector(cpu_dat_width-1 downto 0); |
signal pal_ack_o: std_logic; |
|
signal i_video_out: std_logic_vector (v_pal_size-1 downto 0); |
signal i_blank: std_logic; |
signal vmem_stb: std_logic; |
|
signal vm_cyc: std_logic; |
signal vm_we: std_logic; |
signal vm_stb: std_logic; |
signal vm_ack: std_logic; |
signal vm_adr: std_logic_vector(v_adr_width-bus_resize2adr_bits(cpu_dat_width,v_dat_width)-1 downto 0); |
signal vm_sel: std_logic_vector(cpu_dat_width/8-1 downto 0); |
signal vm_dat_i: std_logic_vector(cpu_dat_width-1 downto 0); |
signal vm_dat_o: std_logic_vector(cpu_dat_width-1 downto 0); |
|
constant vga_reg_size: integer := size2bits((32*8)/cpu_dat_width)-1; |
begin |
core : vga_core |
port map ( |
clk_i => clk_i, |
clk_en => clk_en, |
rst_i => rst_i, |
-- CPU bus interface |
vmem_cyc_i => vm_cyc, |
vmem_we_i => vm_we, |
vmem_stb_i => vm_stb, |
vmem_ack_o => vm_ack, |
vmem_ack_oi => '1', |
vmem_adr_i => vm_adr, |
vmem_sel_i => vm_sel, |
vmem_dat_i => vm_dat_i, |
vmem_dat_oi => (cpu_dat_width-1 downto 0 => '-'), |
vmem_dat_o => vm_dat_o, |
|
-- CPU register bus interface |
reg_cyc_i => cyc_i, |
reg_we_i => we_i, |
reg_stb_i => vga_reg_stb, |
reg_ack_o => vreg_ack_o, |
reg_ack_oi => ack_oi, |
reg_adr_i => adr_i, |
reg_sel_i => sel_i, |
reg_dat_i => dat_i, |
reg_dat_oi => dat_oi, |
reg_dat_o => vreg_dat_o, |
|
|
-- video memory interface |
v_adr_o => v_adr_o, |
v_sel_o => v_sel_o, |
v_dat_i => v_dat_i, |
v_dat_o => v_dat_o, |
v_cyc_o => v_cyc_o, |
v_ack_i => v_ack_i, |
v_we_o => v_we_o, |
v_stb_o => v_stb_o, |
|
h_sync => h_sync, |
h_blank => h_blank, |
v_sync => v_sync, |
v_blank => v_blank, |
h_tc => h_tc, |
v_tc => v_tc, |
blank => i_blank, |
video_out => i_video_out |
); |
|
acc: accel |
port map ( |
clk_i => clk_i, |
rst_i => rst_i, |
|
-- Slave interface to the CPU side |
we_i => we_i, |
cyc_i => cyc_i, |
cur_stb_i => cur_stb, |
ext_stb_i => ext_stb, |
acc_stb_i => acc_stb, |
mem_stb_i => mem_stb, |
|
sel_i => sel_i, |
adr_i => adr_i(accel_size-1 downto 0), |
dat_i => dat_i, |
dat_o => accel_dat_o, |
dat_oi => vreg_dat_o, |
|
ack_o => accel_ack_o, |
ack_oi => vreg_ack_o, |
|
-- Master interface to the video memory side. |
v_we_o => vm_we, |
v_cyc_o => vm_cyc, |
v_stb_o => vm_stb, |
|
v_adr_o => vm_adr, |
v_sel_o => vm_sel, |
v_dat_o => vm_dat_i, |
v_dat_i => vm_dat_o, |
|
v_ack_i => vm_ack |
); |
|
palette: wb_pal_ram |
port map ( |
clk_i => clk_i, |
rst_i => rst_i, |
adr_i => adr_i(v_pal_size-bus_resize2adr_bits(cpu_dat_width,v_dat_width)-1 downto 0), |
dat_i => dat_i, |
dat_oi => accel_dat_o, |
dat_o => dat_o, |
cyc_i => cyc_i, |
ack_o => ack_o, |
ack_oi => accel_ack_o, |
err_o => err_o, |
err_oi => err_oi, |
we_i => we_i, |
stb_i => pal_stb_i, |
-- Interface to the video output |
blank => i_blank, |
v_dat_i => i_video_out, |
v_dat_o => true_color_out |
); |
video_out <= i_video_out; |
blank <= i_blank; |
|
reg_addr_decoder: process is |
begin |
wait on reg_stb_i, adr_i; |
|
vga_reg_stb <= '0'; |
cur_stb <= '0'; |
ext_stb <= '0'; |
|
if (reg_stb_i = '1') then |
case (adr_i(vga_reg_size)) is |
when '0' => vga_reg_stb <= '1'; |
when '1' => |
if (adr_i(vga_reg_size-2) = '1') then |
case (adr_i(vga_reg_size-3)) is |
when '0' => cur_stb <= '1'; |
when '1' => ext_stb <= '1'; |
when others => |
end case; |
end if; |
when others => |
end case; |
end if; |
end process; |
|
accel_addr_decoder: process is |
begin |
wait on accel_stb_i, adr_i; |
|
acc_stb <= '0'; |
mem_stb <= '0'; |
|
if (accel_stb_i = '1') then |
case (adr_i(accel_size)) is |
when '0' => acc_stb <= '1'; |
when '1' => mem_stb <= '1'; |
when others => |
end case; |
end if; |
end process; |
|
end vga_core_v2; |
/wb_vga/trunk/hv_sync.vhd
0,0 → 1,149
-- |
-- Horizontal and vertical sync generator. |
-- |
-- (c) Copyright Andras Tantos <tantos@opencores.org> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
entity hv_sync is |
port ( |
clk: in std_logic; |
pix_clk_en: in std_logic := '1'; |
reset: in std_logic := '0'; |
|
hbs: in std_logic_vector(7 downto 0); |
hss: in std_logic_vector(7 downto 0); |
hse: in std_logic_vector(7 downto 0); |
htotal: in std_logic_vector(7 downto 0); |
vbs: in std_logic_vector(7 downto 0); |
vss: in std_logic_vector(7 downto 0); |
vse: in std_logic_vector(7 downto 0); |
vtotal: in std_logic_vector(7 downto 0); |
|
h_sync: out std_logic; |
h_blank: out std_logic; |
v_sync: out std_logic; |
v_blank: out std_logic; |
h_tc: out std_logic; |
v_tc: out std_logic; |
blank: out std_logic |
); |
end hv_sync; |
|
architecture hv_sync of hv_sync is |
component sync_gen |
port ( |
clk: in std_logic; |
clk_en: in std_logic; |
reset: in std_logic := '0'; |
|
bs: in std_logic_vector(7 downto 0); |
ss: in std_logic_vector(7 downto 0); |
se: in std_logic_vector(7 downto 0); |
total: in std_logic_vector(7 downto 0); |
|
sync: out std_logic; |
blank: out std_logic; |
tc: out std_logic; |
|
count: out std_logic_vector (7 downto 0) |
); |
end component; |
signal h_blank_i: std_logic; |
signal v_blank_i: std_logic; |
signal h_tc_i: std_logic; |
signal hcen: std_logic; |
signal vcen: std_logic; |
|
constant h_pre_div_factor: integer := 3; |
constant v_pre_div_factor: integer := 3; |
subtype h_div_var is integer range 0 to h_pre_div_factor; |
subtype v_div_var is integer range 0 to v_pre_div_factor; |
|
begin |
|
h_pre_div : process is |
variable cntr: h_div_var; |
begin |
wait until clk'EVENT and clk='1'; |
if (reset = '1') then |
cntr := 0; |
hcen <= '0'; |
else |
if (pix_clk_en='1') then |
if (cntr = h_pre_div_factor) then |
cntr := 0; |
hcen <= '1'; |
else |
cntr := cntr+1; |
hcen <= '0'; |
end if; |
else |
hcen <= '0'; |
end if; |
end if; |
end process; |
|
h_sync_gen : sync_gen |
port map ( |
clk => clk, |
clk_en => hcen, |
reset => reset, |
|
bs => hbs, |
ss => hss, |
se => hse, |
total => htotal, |
|
sync => h_sync, |
blank => h_blank_i, |
tc => h_tc_i |
); |
|
h_tc <= h_tc_i; |
|
v_pre_div : process is |
variable cntr: v_div_var; |
begin |
wait until clk'EVENT and clk='1'; |
if (reset = '1') then |
cntr := 0; |
vcen <= '0'; |
else |
if (h_tc_i='1') then |
if (cntr = v_pre_div_factor) then |
cntr := 0; |
vcen <= '1'; |
else |
cntr := cntr+1; |
vcen <= '0'; |
end if; |
else |
vcen <= '0'; |
end if; |
end if; |
end process; |
|
v_sync_gen : sync_gen |
port map ( |
clk => clk, |
clk_en => vcen, |
reset => reset, |
|
bs => vbs, |
ss => vss, |
se => vse, |
total => vtotal, |
|
sync => v_sync, |
blank => v_blank_i, |
tc => v_tc |
); |
|
blank <= h_blank_i or v_blank_i; |
h_blank <= h_blank_i; |
v_blank <= v_blank_i; |
end hv_sync; |
/wb_vga/trunk/sync_gen.vhd
0,0 → 1,80
-- |
-- Programmable sync generator. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
|
-- Standard library. |
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.numeric_std.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
|
entity sync_gen is |
port ( |
clk: in std_logic; |
clk_en: in std_logic; |
reset: in std_logic := '0'; |
|
bs: in std_logic_vector(7 downto 0); |
ss: in std_logic_vector(7 downto 0); |
se: in std_logic_vector(7 downto 0); |
total: in std_logic_vector(7 downto 0); |
|
sync: out std_logic; |
blank: out std_logic; |
tc: out std_logic; |
|
count: out std_logic_vector (7 downto 0) |
); |
end sync_gen; |
|
architecture sync_gen of sync_gen is |
begin |
-- And the sequential machine generating the output signals. |
generator: process is |
variable state: std_logic_vector(7 downto 0); |
begin |
wait until clk'event and clk='1'; |
if (reset = '1') then |
tc <= '0'; |
state := (others => '0'); |
sync <= '0'; |
tc <= '0'; |
blank <= '1'; |
else |
if (clk_en='1') then |
if (state = bs) then |
sync <= '0'; |
blank <= '1'; |
tc <= '0'; |
state := add_one(state); |
elsif (state = ss) then |
sync <= '1'; |
blank <= '1'; |
tc <= '1'; |
state := add_one(state); |
elsif (state = se) then |
sync <= '0'; |
blank <= '1'; |
tc <= '0'; |
state := add_one(state); |
elsif (state = total) then |
sync <= '0'; |
blank <= '0'; |
tc <= '0'; |
state := (others => '0'); |
else |
tc <= '0'; |
state := add_one(state); |
end if; |
count <= state; |
else |
tc <= '0'; |
end if; |
end if; |
end process; |
end sync_gen; |
/wb_vga/trunk/wb_io_reg.vhd
0,0 → 1,104
-- |
-- Wishbone bus toolkit. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
-- |
-- ELEMENTS: |
-- wb_io_reg: A slightly modified version of the wb_out_reg component |
|
------------------------------------------------------------------------------- |
-- |
-- wb_io_reg. A slightly modified version of the wb_out_reg component |
-- |
------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.STD_LOGIC_UNSIGNED.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
|
entity wb_io_reg is |
generic ( |
width : positive := 8; |
bus_width: positive := 8; |
offset: integer := 0 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic; |
rst_val: std_logic_vector(width-1 downto 0) := (others => '0'); |
|
cyc_i: in std_logic := '1'; |
stb_i: in std_logic; |
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1'); |
we_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0'); |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
q: out std_logic_vector (width-1 downto 0); |
ext_d: in std_logic_vector (width-1 downto 0) := (others => '-'); |
ext_we: in std_logic := '0' |
); |
end wb_io_reg; |
|
architecture wb_io_reg of wb_io_reg is |
signal content : std_logic_vector (width-1 downto 0); |
begin |
-- output bus handling with logic |
gen_dat_o: process is |
variable rd_sel: std_logic; |
variable adr: integer; |
variable reg_i: integer; |
begin |
wait on dat_oi, we_i, stb_i, content, adr_i, cyc_i, sel_i; |
rd_sel := cyc_i and stb_i and not we_i; |
for i in dat_i'RANGE loop |
adr := CONV_INTEGER(adr_i); |
reg_i := i-offset+adr*bus_width; |
if ((reg_i >= 0) and (reg_i < width) and (sel_i(i/8) = '1')) then |
dat_o(i) <= (dat_oi(i) and not rd_sel) or (content(reg_i) and rd_sel); |
else |
dat_o(i) <= dat_oi(i); |
end if; |
end loop; |
end process; |
|
-- this item never generates any wait-states unless an external write is under process |
-- ack_o <= (stb_i or ack_oi) and (not (ext_we and we_i)); |
ack_o <= (ack_oi and not stb_i) or ((not (ext_we and we_i)) and stb_i); |
-- ack_o <= (stb_i or ack_oi); |
|
reg: process is |
variable adr: integer; |
variable reg_i: integer; |
begin |
wait until clk_i'EVENT and clk_i='1'; |
if (rst_i = '1') then |
content <= rst_val; |
else |
if (ext_we = '1') then |
content <= ext_d; |
else |
if (stb_i = '1' and cyc_i = '1' and we_i = '1') then |
for i in dat_i'RANGE loop |
adr := CONV_INTEGER(adr_i); |
reg_i := i-offset+adr*bus_width; |
if ((reg_i >= 0) and (reg_i < width) and (sel_i(i/8) = '1')) then |
content(reg_i) <= dat_i(i); |
end if; |
end loop; |
end if; |
end if; |
end if; |
end process; |
q <= content; |
end wb_io_reg; |
|
|
/wb_vga/trunk/Makefile
0,0 → 1,2
all: |
bash compile.sh |
/wb_vga/trunk/palette.vhd
0,0 → 1,168
-- |
-- Palette RAM. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
|
------------------------------------------------------------------------------- |
-- |
-- wb_pal_ram |
-- |
------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library wb_tk; |
use wb_tk.technology.all; |
use wb_tk.all; |
|
entity wb_pal_ram is |
generic ( |
cpu_dat_width: positive := 8; |
cpu_adr_width: positive := 9; |
v_dat_width: positive := 16; |
v_adr_width: positive := 8 |
); |
port ( |
-- Wishbone interface to CPU (write-only support) |
clk_i: in std_logic; |
rst_i: in std_logic := '0'; |
adr_i: in std_logic_vector (cpu_adr_width-1 downto 0); |
-- sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1'); |
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0); |
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0); |
cyc_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
err_o: out std_logic; |
err_oi: in std_logic := '-'; |
-- rty_o: out std_logic; |
-- rty_oi: in std_logic := '-'; |
we_i: in std_logic; |
stb_i: in std_logic; |
-- Interface to the video output |
blank: in std_logic; |
v_dat_i: in std_logic_vector(v_adr_width-1 downto 0); |
v_dat_o: out std_logic_vector(v_dat_width-1 downto 0) |
); |
end wb_pal_ram; |
|
architecture wb_pal_ram of wb_pal_ram is |
component dpram |
generic ( |
data_width : positive; |
addr_width : positive |
); |
port ( |
clk : in std_logic; |
|
r_d_out : out std_logic_vector(data_width-1 downto 0); |
r_rd : in std_logic; |
r_clk_en : in std_logic; |
r_addr : in std_logic_vector(addr_width-1 downto 0); |
|
w_d_in : in std_logic_vector(data_width-1 downto 0); |
w_wr : in std_logic; |
w_clk_en : in std_logic; |
w_addr : in std_logic_vector(addr_width-1 downto 0) |
); |
end component; |
|
component wb_out_reg |
generic ( |
width : positive := 8; |
bus_width: positive := 8; |
offset: integer := 0 |
); |
port ( |
clk_i: in std_logic; |
rst_i: in std_logic; |
rst_val: std_logic_vector(width-1 downto 0) := (others => '0'); |
|
cyc_i: in std_logic := '1'; |
stb_i: in std_logic; |
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1'); |
we_i: in std_logic; |
ack_o: out std_logic; |
ack_oi: in std_logic := '-'; |
adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0'); |
dat_i: in std_logic_vector (bus_width-1 downto 0); |
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-'); |
dat_o: out std_logic_vector (bus_width-1 downto 0); |
q: out std_logic_vector (width-1 downto 0) |
); |
end component; |
|
signal mem_we: std_logic; |
signal mem_rd: std_logic; |
signal mem_d_in: std_logic_vector(v_dat_width-1 downto 0); |
signal ext_reg_stb: std_logic; |
signal mem_stb: std_logic; |
signal mem_d_out: std_logic_vector(v_dat_width-1 downto 0); |
begin |
mem_stb_gen1: if (cpu_dat_width < v_dat_width) generate |
mem_stb <= '1' WHEN adr_i(cpu_adr_width-v_adr_width-1 downto 0)=(cpu_adr_width-v_adr_width-1 downto 0 =>'1') ELSE '0'; |
end generate; |
mem_stb_gen2: if (cpu_dat_width >= v_dat_width) generate |
mem_stb <= '1'; |
end generate; |
mem_we <= we_i and stb_i and cyc_i and mem_stb; |
mem_rd <= not blank; |
mem_d_in_gen1: if (cpu_dat_width < v_dat_width) generate |
mem_d_in(v_dat_width-1 downto v_dat_width-cpu_dat_width) <= dat_i; |
end generate; |
mem_d_in_gen2: if (cpu_dat_width >= v_dat_width) generate |
mem_d_in(v_dat_width-1 downto 0) <= dat_i(mem_d_in'RANGE); |
end generate; |
tech_ram: dpram |
generic map( |
data_width => v_dat_width, |
addr_width => v_adr_width |
) |
port map ( |
clk => clk_i, |
|
r_d_out => mem_d_out, |
r_rd => mem_rd, |
r_clk_en => '1', |
r_addr => v_dat_i, |
|
w_d_in => mem_d_in, |
w_wr => mem_we, |
w_clk_en => '1', |
w_addr => adr_i(cpu_adr_width-1 downto cpu_adr_width-v_adr_width) |
); |
v_dat_o_gen: for i in v_dat_o'RANGE generate |
v_dat_o(i) <= mem_d_out(i) and not blank; |
end generate; |
|
ext_reg_stb <= we_i and stb_i and cyc_i and not mem_stb; |
ext_reg_gen: if (cpu_dat_width < v_dat_width) generate |
ext_reg: wb_out_reg |
generic map ( |
width => v_dat_width-cpu_dat_width, |
bus_width => cpu_dat_width, |
offset => 0 |
) |
port map ( |
clk_i => clk_i, |
rst_i => rst_i, |
|
cyc_i => cyc_i, |
stb_i => ext_reg_stb, |
we_i => we_i, |
-- ack_o |
adr_i => adr_i(cpu_adr_width-v_adr_width-1 downto 0), |
dat_i => dat_i, |
q => mem_d_in(v_dat_width-cpu_dat_width-1 downto 0) |
); |
end generate; |
|
dat_o <= dat_oi; |
ack_o <= ( we_i and (stb_i and cyc_i)) or (ack_oi and not (stb_i and cyc_i)); |
err_o <= ((not we_i) and (stb_i and cyc_i)) or (err_oi and not (stb_i and cyc_i)); |
end wb_pal_ram; |
|
/wb_vga/trunk/gpl.txt
0,0 → 1,221
GNU GENERAL PUBLIC LICENSE |
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION |
|
0. This License applies to any program or other work which contains |
a notice placed by the copyright holder saying it may be distributed |
under the terms of this General Public License. The "Program", below, |
refers to any such program or work, and a "work based on the Program" |
means either the Program or any derivative work under copyright law: |
that is to say, a work containing the Program or a portion of it, |
either verbatim or with modifications and/or translated into another |
language. (Hereinafter, translation is included without limitation in |
the term "modification".) Each licensee is addressed as "you". |
|
Activities other than copying, distribution and modification are not |
covered by this License; they are outside its scope. The act of |
running the Program is not restricted, and the output from the Program |
is covered only if its contents constitute a work based on the |
Program (independent of having been made by running the Program). |
Whether that is true depends on what the Program does. |
|
1. You may copy and distribute verbatim copies of the Program's |
source code as you receive it, in any medium, provided that you |
conspicuously and appropriately publish on each copy an appropriate |
copyright notice and disclaimer of warranty; keep intact all the |
notices that refer to this License and to the absence of any warranty; |
and give any other recipients of the Program a copy of this License |
along with the Program. |
|
You may charge a fee for the physical act of transferring a copy, and |
you may at your option offer warranty protection in exchange for a fee. |
|
2. You may modify your copy or copies of the Program or any portion |
of it, thus forming a work based on the Program, and copy and |
distribute such modifications or work under the terms of Section 1 |
above, provided that you also meet all of these conditions: |
|
a) You must cause the modified files to carry prominent notices |
stating that you changed the files and the date of any change. |
|
b) You must cause any work that you distribute or publish, that in |
whole or in part contains or is derived from the Program or any |
part thereof, to be licensed as a whole at no charge to all third |
parties under the terms of this License. |
|
c) If the modified program normally reads commands interactively |
when run, you must cause it, when started running for such |
interactive use in the most ordinary way, to print or display an |
announcement including an appropriate copyright notice and a |
notice that there is no warranty (or else, saying that you provide |
a warranty) and that users may redistribute the program under |
these conditions, and telling the user how to view a copy of this |
License. (Exception: if the Program itself is interactive but |
does not normally print such an announcement, your work based on |
the Program is not required to print an announcement.) |
|
These requirements apply to the modified work as a whole. If |
identifiable sections of that work are not derived from the Program, |
and can be reasonably considered independent and separate works in |
themselves, then this License, and its terms, do not apply to those |
sections when you distribute them as separate works. But when you |
distribute the same sections as part of a whole which is a work based |
on the Program, the distribution of the whole must be on the terms of |
this License, whose permissions for other licensees extend to the |
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|
Thus, it is not the intent of this section to claim rights or contest |
your rights to work written entirely by you; rather, the intent is to |
exercise the right to control the distribution of derivative or |
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|
In addition, mere aggregation of another work not based on the Program |
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|
3. You may copy and distribute the Program (or a work based on it, |
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|
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b) Accompany it with a written offer, valid for at least three |
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cost of physically performing source distribution, a complete |
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|
c) Accompany it with the information you received as to the offer |
to distribute corresponding source code. (This alternative is |
allowed only for noncommercial distribution and only if you |
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|
The source code for a work means the preferred form of the work for |
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If distribution of executable or object code is made by offering |
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compelled to copy the source along with the object code. |
|
4. You may not copy, modify, sublicense, or distribute the Program |
except as expressly provided under this License. Any attempt |
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|
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the Program or works based on it. |
|
6. Each time you redistribute the Program (or any work based on the |
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|
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|
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|
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|
This section is intended to make thoroughly clear what is believed to |
be a consequence of the rest of this License. |
|
8. If the distribution and/or use of the Program is restricted in |
certain countries either by patents or by copyrighted interfaces, the |
original copyright holder who places the Program under this License |
may add an explicit geographical distribution limitation excluding |
those countries, so that distribution is permitted only in or among |
countries not thus excluded. In such case, this License incorporates |
the limitation as if written in the body of this License. |
|
9. The Free Software Foundation may publish revised and/or new versions |
of the General Public License from time to time. Such new versions will |
be similar in spirit to the present version, but may differ in detail to |
address new problems or concerns. |
|
Each version is given a distinguishing version number. If the Program |
specifies a version number of this License which applies to it and "any |
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10. If you wish to incorporate parts of the Program into other free |
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NO WARRANTY |
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11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY |
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN |
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES |
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED |
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12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING |
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POSSIBILITY OF SUCH DAMAGES. |
|
/wb_vga/trunk/technology.vhd
0,0 → 1,194
-- |
-- Technology mapping library. ALTERA edition. |
-- |
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31 |
-- This code is distributed under the terms and conditions of the GNU General Public Lince. |
-- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
library exemplar; |
use exemplar.exemplar_1164.all; |
|
package technology is |
function add_one(inp : std_logic_vector) return std_logic_vector; |
function is_zero(inp : std_logic_vector) return boolean; |
function sl(l: std_logic_vector; r: integer) return std_logic_vector; |
-- procedure inc(data : inout std_logic_vector); |
function "+"(op_l, op_r: std_logic_vector) return std_logic_vector; |
|
component d_ff is |
port ( d : in STD_LOGIC; |
clk: in STD_LOGIC; |
ena: in STD_LOGIC := '1'; |
clr: in STD_LOGIC := '0'; |
pre: in STD_LOGIC := '0'; |
q : out STD_LOGIC |
); |
end component; |
component fifo is |
generic (fifo_width : positive; |
used_width : positive; |
fifo_depth : positive |
); |
port (d_in : in std_logic_vector(fifo_width-1 downto 0); |
clk : in std_logic; |
wr : in std_logic; |
rd : in std_logic; |
a_clr : in std_logic := '0'; |
s_clr : in std_logic := '0'; |
d_out : out std_logic_vector(fifo_width-1 downto 0); |
used : out std_logic_vector(used_width-1 downto 0); |
full : out std_logic; |
empty : out std_logic |
); |
end component; |
end technology; |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
library exemplar; |
use exemplar.exemplar_1164.all; |
|
package body technology is |
function "+"(op_l, op_r: std_logic_vector) return std_logic_vector is |
begin |
return exemplar_1164."+"(op_l, op_r); |
end; |
|
function add_one(inp : std_logic_vector) return std_logic_vector is |
variable one: std_logic_vector(inp'RANGE) := (others => '0'); |
begin |
one(0) := '1'; |
return exemplar_1164."+"(inp,one); |
end; |
|
function is_zero(inp : std_logic_vector) return boolean is |
variable zero: std_logic_vector(inp'RANGE) := (others => '0'); |
begin |
return (inp = zero); |
end; |
|
function sl(l: std_logic_vector; r: integer) return std_logic_vector is |
begin |
return exemplar_1164.sl(l,r); |
end; |
-- procedure inc(data : inout std_logic_vector) is |
-- begin |
-- data := addone(data); |
-- end; |
end package body technology; |
|
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library exemplar; |
use exemplar.exemplar_1164.all; |
|
library lpm; |
use lpm.all; |
|
entity fifo is |
generic (fifo_width : positive; |
used_width : positive; |
fifo_depth : positive |
); |
port (d_in : in std_logic_vector(fifo_width-1 downto 0); |
clk : in std_logic; |
wr : in std_logic; |
rd : in std_logic; |
a_clr : in std_logic := '0'; |
s_clr : in std_logic := '0'; |
d_out : out std_logic_vector(fifo_width-1 downto 0); |
used : out std_logic_vector(used_width-1 downto 0); |
full : out std_logic; |
empty : out std_logic |
); |
end fifo; |
|
architecture altera of fifo is |
component lpm_fifo |
generic (LPM_WIDTH : positive; |
LPM_WIDTHU : positive; |
LPM_NUMWORDS : positive; |
LPM_SHOWAHEAD : string := "OFF"; |
LPM_TYPE : string := "LPM_FIFO"; |
LPM_HINT : string := "UNUSED"); |
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0); |
CLOCK : in std_logic; |
WRREQ : in std_logic; |
RDREQ : in std_logic; |
ACLR : in std_logic; |
SCLR : in std_logic; |
Q : out std_logic_vector(LPM_WIDTH-1 downto 0); |
USEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0); |
FULL : out std_logic; |
EMPTY : out std_logic); |
end component; |
begin |
altera_fifo: lpm_fifo |
generic map ( |
LPM_WIDTH => fifo_width, |
LPM_WIDTHU => used_width, |
LPM_NUMWORDS => fifo_depth, |
LPM_SHOWAHEAD => "OFF", |
LPM_TYPE => "LPM_FIFO", |
LPM_HINT => "UNUSED" |
) |
port map ( |
DATA => d_in, |
CLOCK => clk, |
WRREQ => wr, |
RDREQ => rd, |
ACLR => a_clr, |
SCLR => s_clr, |
Q => d_out, |
USEDW => used, |
FULL => full, |
EMPTY => empty |
); |
end altera; |
|
|
library IEEE; |
use IEEE.std_logic_1164.all; |
|
library altera_exemplar; |
use altera_exemplar.all; |
|
entity d_ff is |
port ( d : in STD_LOGIC; |
clk: in STD_LOGIC; |
ena: in STD_LOGIC := '1'; |
clr: in STD_LOGIC := '0'; |
pre: in STD_LOGIC := '0'; |
q : out STD_LOGIC |
); |
end d_ff; |
|
architecture altera of d_ff is |
component dffe |
port ( D : in STD_LOGIC; |
CLK: in STD_LOGIC; |
ENA: in STD_LOGIC; |
CLRN: in STD_LOGIC; |
PRN: in STD_LOGIC; |
Q : out STD_LOGIC); |
end component; |
signal clrn,prn: std_logic; |
begin |
clrn <= not clr; |
prn <= not pre; |
ff: dffe port map ( |
D => d, |
CLK => clk, |
ENA => ena, |
CLRN => clrn, |
PRN => prn, |
Q => q |
); |
end altera; |
|
-- Sythetizer library. Contains STD_LOGIC arithmetics |
|
wb_vga/trunk
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: wb_vga/web_uploads
===================================================================
--- wb_vga/web_uploads (nonexistent)
+++ wb_vga/web_uploads (revision 8)
wb_vga/web_uploads
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: wb_vga/branches
===================================================================
--- wb_vga/branches (nonexistent)
+++ wb_vga/branches (revision 8)
wb_vga/branches
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: wb_vga/tags/a01/TestBench/vga_chip_TB.vhd
===================================================================
--- wb_vga/tags/a01/TestBench/vga_chip_TB.vhd (nonexistent)
+++ wb_vga/tags/a01/TestBench/vga_chip_TB.vhd (revision 8)
@@ -0,0 +1,309 @@
+library ieee,exemplar;
+use ieee.std_logic_1164.all;
+use exemplar.exemplar_1164.all;
+
+entity vga_chip_tb is
+ -- Generic declarations of the tested unit
+ generic(
+ v_mem_width : POSITIVE := 16;
+ fifo_size : POSITIVE := 256;
+ v_addr_width : POSITIVE := 20 );
+end vga_chip_tb;
+
+architecture TB of vga_chip_tb is
+ -- Component declaration of the tested unit
+ component vga_chip
+ port (
+ clk_i: in std_logic;
+ clk_en: in std_logic := '1';
+ rst_i: in std_logic := '0';
+
+ -- CPU bus interface
+ dat_i: in std_logic_vector (8-1 downto 0);
+ dat_oi: in std_logic_vector (8-1 downto 0);
+ dat_o: out std_logic_vector (8-1 downto 0);
+ cyc_i: in std_logic;
+ ack_o: out std_logic;
+ ack_oi: in std_logic;
+ we_i: in std_logic;
+ vmem_stb_i: in std_logic;
+ reg_stb_i: in std_logic;
+ adr_i: in std_logic_vector (20 downto 0);
+
+ -- video memory SRAM interface
+ s_data : inout std_logic_vector((16-1) downto 0);
+ s_addr : out std_logic_vector((20-1) downto 0);
+ s_oen : out std_logic;
+ s_wrhn : out std_logic;
+ s_wrln : out std_logic;
+ s_cen : out std_logic;
+
+ -- sync blank and video signal outputs
+ h_sync: out std_logic;
+ h_blank: out std_logic;
+ v_sync: out std_logic;
+ v_blank: out std_logic;
+ h_tc: out std_logic;
+ v_tc: out std_logic;
+ blank: out std_logic;
+ video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
+ );
+ end component;
+
+ -- Stimulus signals - signals mapped to the input and inout ports of tested entity
+ signal clk_i : std_logic;
+ signal clk_en : std_logic;
+ signal rst_i : std_logic;
+ signal dat_i : std_logic_vector(7 downto 0);
+ signal dat_oi : std_logic_vector(7 downto 0);
+ signal cyc_i : std_logic;
+ signal ack_oi : std_logic;
+ signal we_i : std_logic;
+ signal vmem_stb_i : std_logic;
+ signal reg_stb_i : std_logic;
+ signal adr_i : std_logic_vector(v_addr_width downto 0);
+ signal s_data : std_logic_vector((v_mem_width-1) downto 0);
+ -- Observed signals - signals mapped to the output ports of tested entity
+ signal dat_o : std_logic_vector(7 downto 0);
+ signal ack_o : std_logic;
+ signal s_addr : std_logic_vector((v_addr_width-1) downto 0);
+ signal s_oen : std_logic;
+ signal s_wrhn : std_logic;
+ signal s_wrln : std_logic;
+ signal s_cen : std_logic;
+ signal h_sync : std_logic;
+ signal h_blank : std_logic;
+ signal v_sync : std_logic;
+ signal v_blank : std_logic;
+ signal h_tc : std_logic;
+ signal v_tc : std_logic;
+ signal blank : std_logic;
+ signal video_out : std_logic_vector(7 downto 0);
+
+ constant reg_total0 : std_logic_vector(v_addr_width downto 0) := "000000000000000000000";
+ constant reg_total1 : std_logic_vector(v_addr_width downto 0) := "000000000000000000001";
+ constant reg_total2 : std_logic_vector(v_addr_width downto 0) := "000000000000000000010";
+ constant reg_fifo_treshold : std_logic_vector(v_addr_width downto 0) := "000000000000000000011";
+ constant reg_hbs : std_logic_vector(v_addr_width downto 0) := "000000000000000000100";
+ constant reg_hss : std_logic_vector(v_addr_width downto 0) := "000000000000000000101";
+ constant reg_hse : std_logic_vector(v_addr_width downto 0) := "000000000000000000110";
+ constant reg_htotal : std_logic_vector(v_addr_width downto 0) := "000000000000000000111";
+ constant reg_vbs : std_logic_vector(v_addr_width downto 0) := "000000000000000001000";
+ constant reg_vss : std_logic_vector(v_addr_width downto 0) := "000000000000000001001";
+ constant reg_vse : std_logic_vector(v_addr_width downto 0) := "000000000000000001010";
+ constant reg_vtotal : std_logic_vector(v_addr_width downto 0) := "000000000000000001011";
+ constant reg_pps : std_logic_vector(v_addr_width downto 0) := "000000000000000001100";
+ constant reg_ws : std_logic_vector(v_addr_width downto 0) := "000000000000000001101";
+ constant reg_bpp : std_logic_vector(v_addr_width downto 0) := "000000000000000001110";
+
+ constant val_total0 : std_logic_vector(7 downto 0) := "00001111";
+ constant val_total1 : std_logic_vector(7 downto 0) := "00000000";
+ constant val_total2 : std_logic_vector(7 downto 0) := "00000000";
+ constant val_fifo_treshold : std_logic_vector(7 downto 0) := "00000011";
+ constant val_hbs : std_logic_vector(7 downto 0) := "00000111";
+ constant val_hss : std_logic_vector(7 downto 0) := "00001000";
+ constant val_hse : std_logic_vector(7 downto 0) := "00001001";
+ constant val_htotal : std_logic_vector(7 downto 0) := "00001010";
+ constant val_vbs : std_logic_vector(7 downto 0) := "00000001";
+ constant val_vss : std_logic_vector(7 downto 0) := "00000010";
+ constant val_vse : std_logic_vector(7 downto 0) := "00000011";
+ constant val_vtotal : std_logic_vector(7 downto 0) := "00000100";
+ constant val_pps : std_logic_vector(7 downto 0) := "00000001";
+ constant val_ws : std_logic_vector(7 downto 0) := "00010010";
+-- constant val_bpp : std_logic_vector(7 downto 0) := "00000001";
+ constant val_bpp : std_logic_vector(7 downto 0) := "00000011";
+
+ -- Add your code here ...
+
+ procedure chk_val(
+ signal clk_i: in STD_LOGIC;
+ signal adr_i: out STD_LOGIC_VECTOR(v_addr_width downto 0);
+ signal dat_o: in STD_LOGIC_VECTOR(7 downto 0);
+ signal dat_i: out STD_LOGIC_VECTOR(7 downto 0);
+ signal we_i: out STD_LOGIC;
+ signal cyc_i: out std_logic;
+ signal stb_i: out STD_LOGIC;
+ signal ack_o: in STD_LOGIC;
+ constant addr: in STD_LOGIC_VECTOR(v_addr_width downto 0);
+ constant data: in STD_LOGIC_VECTOR(7 downto 0)
+ ) is
+ begin
+ wait until clk_i'EVENT and clk_i = '1';
+ wait until clk_i'EVENT and clk_i = '1';
+ wait until clk_i'EVENT and clk_i = '1';
+ adr_i <= addr;
+ dat_i <= (others => '0');
+ cyc_i <= '1';
+ stb_i <= '1';
+ we_i <= '0';
+ wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
+ assert dat_o = data report "Value does not match!" severity ERROR;
+ adr_i <= (others => '0');
+ stb_i <= '0';
+ cyc_i <= '0';
+ end procedure;
+
+ procedure write_val(
+ signal clk_i: in STD_LOGIC;
+ signal adr_i: out STD_LOGIC_VECTOR(v_addr_width downto 0);
+ signal dat_o: in STD_LOGIC_VECTOR(7 downto 0);
+ signal dat_i: out STD_LOGIC_VECTOR(7 downto 0);
+ signal we_i: out STD_LOGIC;
+ signal cyc_i: out std_logic;
+ signal stb_i: out STD_LOGIC;
+ signal ack_o: in STD_LOGIC;
+ constant addr: in STD_LOGIC_VECTOR(v_addr_width downto 0);
+ constant data: in STD_LOGIC_VECTOR(7 downto 0)
+ ) is
+ begin
+ adr_i <= (others => '0');
+ dat_i <= (others => '0');
+ stb_i <= '0';
+ we_i <= '0';
+ wait until clk_i'EVENT and clk_i = '1';
+ wait until clk_i'EVENT and clk_i = '1';
+ wait until clk_i'EVENT and clk_i = '1';
+ adr_i <= addr;
+ dat_i <= data;
+ cyc_i <= '1';
+ stb_i <= '1';
+ we_i <= '1';
+ wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
+ adr_i <= (others => '0');
+ dat_i <= (others => '0');
+ cyc_i <= '0';
+ stb_i <= '0';
+ we_i <= '0';
+ end procedure;
+begin
+
+ -- Unit Under Test port map
+ UUT : vga_chip
+ port map (
+ clk_i => clk_i,
+ clk_en => clk_en,
+ rst_i => rst_i,
+ dat_i => dat_i,
+ dat_oi => dat_oi,
+ dat_o => dat_o,
+ cyc_i => cyc_i,
+ ack_o => ack_o,
+ ack_oi => ack_oi,
+ we_i => we_i,
+ vmem_stb_i => vmem_stb_i,
+ reg_stb_i => reg_stb_i,
+ adr_i => adr_i,
+ s_data => s_data,
+ s_addr => s_addr,
+ s_oen => s_oen,
+ s_wrhn => s_wrhn,
+ s_wrln => s_wrln,
+ s_cen => s_cen,
+ h_sync => h_sync,
+ h_blank => h_blank,
+ v_sync => v_sync,
+ v_blank => v_blank,
+ h_tc => h_tc,
+ v_tc => v_tc,
+ blank => blank,
+ video_out => video_out
+ );
+
+ -- Add your stimulus here ...
+
+ clk_en <= '1';
+ -- Add your stimulus here ...
+ clock: process is
+ begin
+ wait for 25 ns;
+ clk_i <= '1';
+ wait for 25 ns;
+ clk_i <= '0';
+ end process;
+
+ ack_oi <= '0';
+ dat_oi <= (others => '0');
+
+ setup: process is
+ begin
+ we_i <= '0';
+ reg_stb_i <= '0';
+ vmem_stb_i <= '0';
+ rst_i <= '1';
+ wait until clk_i'EVENT and clk_i = '1';
+ wait until clk_i'EVENT and clk_i = '1';
+ rst_i <= '0';
+ wait until clk_i'EVENT and clk_i = '1';
+ wait until clk_i'EVENT and clk_i = '1';
+ wait until clk_i'EVENT and clk_i = '1';
+ wait until clk_i'EVENT and clk_i = '1';
+
+ write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0 ,val_total0);
+ write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total1 ,val_total1);
+ write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2 ,val_total2);
+ write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold ,val_fifo_treshold);
+ write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs ,val_hbs);
+ write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hss ,val_hss);
+ write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse ,val_hse);
+ write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_htotal ,val_htotal);
+ write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs ,val_vbs);
+ write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vss ,val_vss);
+ write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse ,val_vse);
+ write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vtotal ,val_vtotal);
+ write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps ,val_pps);
+ write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws ,val_ws);
+ write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_bpp ,val_bpp);
+
+ wait until clk_i'EVENT and clk_i = '1';
+ wait until clk_i'EVENT and clk_i = '1';
+ wait until clk_i'EVENT and clk_i = '1';
+ wait until clk_i'EVENT and clk_i = '1';
+ wait until clk_i'EVENT and clk_i = '1';
+ wait until clk_i'EVENT and clk_i = '1';
+ wait until clk_i'EVENT and clk_i = '1';
+
+ chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0 ,val_total0);
+ chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total1 ,val_total1);
+ chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2 ,val_total2);
+ chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold ,val_fifo_treshold);
+ chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs ,val_hbs);
+ chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hss ,val_hss);
+ chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse ,val_hse);
+ chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_htotal ,val_htotal);
+ chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs ,val_vbs);
+ chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vss ,val_vss);
+ chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse ,val_vse);
+ chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vtotal ,val_vtotal);
+ chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps ,val_pps);
+ chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws ,val_ws);
+ chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_bpp ,val_bpp);
+
+ wait;
+ end process;
+
+ s_ram: process is
+ begin
+ wait on s_data,s_addr,s_oen,s_wrhn,s_wrln,s_cen;
+ if (s_cen = '0') then
+ if (s_oen = '0') then
+ s_data <= s_addr(v_mem_width-1 downto 0);
+ elsif (s_wrhn = '0' or s_wrln = '0') then
+ if (s_wrhn = '0') then
+ else
+ end if;
+ else
+ s_data <= (others => 'Z');
+ end if;
+ end if;
+ end process;
+
+end TB;
+
+configuration TB_vga_chip of vga_chip_tb is
+ for TB
+ for UUT : vga_chip
+ use entity work.vga_chip(vga_chip);
+ end for;
+ end for;
+end TB_vga_chip;
+
Index: wb_vga/tags/a01/gpl.txt
===================================================================
--- wb_vga/tags/a01/gpl.txt (nonexistent)
+++ wb_vga/tags/a01/gpl.txt (revision 8)
@@ -0,0 +1,221 @@
+ GNU GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
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+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+ 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
Index: wb_vga/tags/a01/mem_reader.vhd
===================================================================
--- wb_vga/tags/a01/mem_reader.vhd (nonexistent)
+++ wb_vga/tags/a01/mem_reader.vhd (revision 8)
@@ -0,0 +1,347 @@
+--
+-- File: mem_reader.vhd
+--
+-- (c) Copyright Andras Tantos 2001/03/31
+-- This code is distributed under the terms and conditions of the GNU General Public Lince.
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library work;
+use work.technology.all;
+
+entity mem_reader is
+ generic (
+ v_mem_width: positive := 16;
+ v_addr_width: positive:= 20;
+ fifo_size: positive := 256;
+ dual_scan_fifo_size: positive := 256
+ );
+ port (
+ clk: in std_logic;
+ clk_en: in std_logic;
+ pix_clk_en: in std_logic;
+ reset: in std_logic := '0';
+
+ total: in std_logic_vector(v_addr_width-1 downto 0); -- total video memory size in bytes 7..0
+ fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold
+ bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8
+ multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans
+
+ -- Can be githces on it!!! Don't clock by it!!!
+ high_prior: out std_logic; -- signals to the memory arbitrer to give high
+ -- priority to the video engine
+ v_mem_rd: out std_logic; -- video memory read request
+ v_mem_rdy: in std_logic; -- video memory data ready
+ v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address
+ v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data
+
+ blank: in std_logic; -- video sync generator blank output
+ h_tc: in std_logic; -- horizontal sync pulse. Must be 1 clock wide!
+ video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
+ );
+end mem_reader;
+
+architecture mem_reader of mem_reader is
+ component fifo
+ generic (fifo_width : positive;
+ used_width : positive;
+ fifo_depth : positive
+ );
+ port (d_in : in std_logic_vector(fifo_width-1 downto 0);
+ clk : in std_logic;
+ wr : in std_logic;
+ rd : in std_logic;
+ a_clr : in std_logic := '0';
+ s_clr : in std_logic := '0';
+ d_out : out std_logic_vector(fifo_width-1 downto 0);
+ used : out std_logic_vector(used_width-1 downto 0);
+ full : out std_logic;
+ empty : out std_logic
+ );
+ end component;
+
+ signal fifo_rd: std_logic;
+ signal fifo_out: std_logic_vector(v_mem_width-1 downto 0);
+
+ signal video_fifo_out: std_logic_vector(v_mem_width-1 downto 0);
+ signal video_fifo_usedw: std_logic_vector(7 downto 0);
+ signal video_fifo_rd: std_logic;
+ signal video_fifo_full: std_logic;
+ signal video_fifo_empty: std_logic;
+
+ signal ds_fifo_out: std_logic_vector(v_mem_width-1 downto 0);
+-- signal ds_fifo_usedw: std_logic_vector(7 downto 0);
+ signal ds_fifo_rd: std_logic;
+ signal ds_fifo_clr: std_logic;
+-- signal ds_fifo_full: std_logic;
+-- signal ds_fifo_empty: std_logic;
+
+ signal i_video_out: std_logic_vector(7 downto 0);
+ signal ds_mode: std_logic;
+
+ subtype pixel_cntr_var is integer range 0 to 7;
+
+-- signal i_v_mem_rd: std_logic := '0';
+
+begin
+ -- memory decoupler FIFO
+ pixel_fifo: fifo
+ generic map (
+ fifo_width => v_mem_width,
+ used_width => 8,
+ fifo_depth => fifo_size
+ )
+ port map (
+ d_in => v_mem_data,
+ clk => clk,
+ wr => v_mem_rdy,
+ rd => video_fifo_rd,
+-- a_clr => '0',
+ a_clr => reset,
+ s_clr => reset,
+ full => video_fifo_full,
+ d_out => video_fifo_out,
+ used => video_fifo_usedw,
+ empty => video_fifo_empty
+ );
+
+ -- dual-scan FIFO
+ ds_pixel_fifo: fifo
+ generic map (
+ fifo_width => v_mem_width,
+ used_width => 8,
+ fifo_depth => dual_scan_fifo_size
+ )
+ port map (
+ d_in => fifo_out,
+ clk => clk,
+ wr => fifo_rd,
+ rd => ds_fifo_rd,
+-- a_clr => '0',
+ a_clr => reset,
+ s_clr => ds_fifo_clr,
+ d_out => ds_fifo_out
+ );
+
+ -- Multiplexer for DS data handling
+ fifo_mux: for i in v_mem_width-1 downto 0 generate
+ begin
+ fifo_out(i) <= (video_fifo_out(i) and not ds_mode) or (ds_fifo_out(i) and ds_mode);
+-- fifo_out(i) <= (video_fifo_out(i) and not ds_mode);
+ end generate;
+ --fifo_out <= (video_fifo_out and not ds_mode);
+ ds_fifo_rd <= ('0' and not ds_mode) or (fifo_rd and ds_mode);
+ video_fifo_rd <= (fifo_rd and not ds_mode) or ('0' and ds_mode);
+
+ -- Counter handles DS
+ ds_counter : process is
+ variable cnt: std_logic_vector(1 downto 0);
+ begin
+ wait until clk'EVENT and clk = '1';
+ if (reset = '1') then
+ cnt := (others => '0');
+ ds_fifo_clr <= '1';
+ ds_mode <= '0';
+ else
+ if (clk_en = '1') then
+ if (h_tc = '1') then
+ if (is_zero(cnt)) then
+ ds_mode <= '0';
+ ds_fifo_clr <= '1';
+ else
+ ds_mode <= '1';
+ ds_fifo_clr <= '0';
+ end if;
+ if (cnt = multi_scan) then
+ cnt := (others => '0');
+ else
+ cnt := add_one(cnt);
+ end if;
+ else
+ ds_fifo_clr <= '0';
+ end if;
+ else
+ ds_fifo_clr <= '1';
+ ds_mode <= '0';
+ end if;
+ end if;
+ end process;
+
+ -- Pixel data reader state machine
+ pixel_cntr : process is
+ variable pixel_cnt: std_logic_vector(v_addr_width-1 downto 0);
+ begin
+ wait until clk'EVENT and clk='1';
+ if (reset = '1') then
+ pixel_cnt := (others => '0');
+ else
+ -- A little cheet. It won't work with constant v_mem_rdy.
+ if (v_mem_rdy = '1') then
+ -- data is already written to the FIFO, all we need to do is to update the counter,
+ -- and remove the request
+ if (pixel_cnt = total) then
+ pixel_cnt := (others => '0');
+ else
+ pixel_cnt := add_one(pixel_cnt);
+ end if;
+ end if;
+ end if;
+ v_mem_addr <= pixel_cnt;
+ end process;
+ v_mem_rd <= not video_fifo_full;
+
+ -- Pixel data output state machine.
+ pixel_output: process is
+ subtype pixel_cntr_var is integer range 0 to v_mem_width-1;
+
+ variable pixel_cntr : pixel_cntr_var;
+ variable shift_reg : std_logic_vector (v_mem_width-1 downto 0);
+ type rst_states is (in_reset,read,normal);
+ variable rst_state : rst_states := in_reset;
+ begin
+ wait until clk'EVENT and clk='1';
+ if (reset = '1') then
+ fifo_rd <= '0';
+ i_video_out <= (others => '0');
+ shift_reg := (others => '0');
+ pixel_cntr := 0;
+ rst_state := in_reset;
+ else
+ if (not (rst_state = normal)) then
+ -- perform one read after reset otherwise the picture will be shifted rigth one pixel
+ case (rst_state) is
+ when in_reset =>
+ if (video_fifo_empty = '0') then
+ fifo_rd <= '1';
+ rst_state := read;
+ else
+ fifo_rd <= '0';
+ end if;
+ when read =>
+ pixel_cntr := 0;
+ shift_reg := fifo_out;
+ fifo_rd <= '0';
+ rst_state := normal;
+ when others =>
+ end case;
+ else
+ if (pix_clk_en = '0') then
+ fifo_rd <= '0'; -- clear any pending read requests
+ else
+ if (blank = '1') then
+ fifo_rd <= '0'; -- clear any pending read requests
+ i_video_out <= (others => '0'); -- disable output
+-- i_video_out <= (others => 'U'); -- disable output
+ else
+ case (bpp) is
+ when "00" =>
+ -- shift next data to the output and optionally read the next data from the fifo
+ i_video_out(0) <= shift_reg(v_mem_width-1);
+ i_video_out(7 downto 1) <= (others => '0');
+ if (pixel_cntr = v_mem_width-1) then
+ -- Read next data
+ pixel_cntr := 0;
+ shift_reg := fifo_out;
+ fifo_rd <= '0';
+ elsif (pixel_cntr = v_mem_width-2) then
+ -- Request next data from FIFO
+ pixel_cntr := pixel_cntr + 1;
+ fifo_rd <= '1';
+ shift_reg := sl(shift_reg,1);
+ else
+ -- Simple increment
+ pixel_cntr := pixel_cntr + 1;
+ fifo_rd <= '0';
+ shift_reg := sl(shift_reg,1);
+ end if;
+ when "01" =>
+ -- shift next data to the output and optionally read the next data from the fifo
+ i_video_out(1 downto 0) <= shift_reg(v_mem_width-1 downto v_mem_width-2);
+ i_video_out(7 downto 2) <= (others => '0');
+ if (pixel_cntr = v_mem_width/2-1) then
+ -- Read next data
+ pixel_cntr := 0;
+ shift_reg := fifo_out;
+ fifo_rd <= '0';
+ elsif (pixel_cntr = v_mem_width/2-2) then
+ -- Request next data from FIFO
+ pixel_cntr := pixel_cntr + 1;
+ fifo_rd <= '1';
+ shift_reg := sl(shift_reg,2);
+ else
+ -- Simple increment
+ pixel_cntr := pixel_cntr + 1;
+ fifo_rd <= '0';
+ shift_reg := sl(shift_reg,2);
+ end if;
+ when "10" =>
+ -- shift next data to the output and optionally read the next data from the fifo
+ i_video_out(3 downto 0) <= shift_reg(v_mem_width-1 downto v_mem_width-4);
+ i_video_out(7 downto 4) <= (others => '0');
+ if (pixel_cntr = v_mem_width/4-1) then
+ -- Read next data
+ pixel_cntr := 0;
+ shift_reg := fifo_out;
+ fifo_rd <= '0';
+ elsif (pixel_cntr = v_mem_width/4-2) then
+ -- Request next data from FIFO
+ pixel_cntr := pixel_cntr + 1;
+ fifo_rd <= '1';
+ shift_reg := sl(shift_reg,4);
+ else
+ -- Simple increment
+ pixel_cntr := pixel_cntr + 1;
+ fifo_rd <= '0';
+ shift_reg := sl(shift_reg,4);
+ end if;
+ when "11" =>
+ if (v_mem_width = 8) then
+ -- 8 bit memory with 8 bit output: every clock reads a byte from the fifo.
+ fifo_rd <= '1';
+ i_video_out(7 downto 0) <= fifo_out;
+ else
+ -- shift next data to the output and optionally read the next data from the fifo
+ i_video_out(7 downto 0) <= shift_reg(v_mem_width-1 downto v_mem_width-8);
+ if (pixel_cntr = v_mem_width/8-1) then
+ -- Read next data
+ pixel_cntr := 0;
+ shift_reg := fifo_out;
+ fifo_rd <= '0';
+ elsif (pixel_cntr = v_mem_width/8-2) then
+ -- Request next data from FIFO
+ pixel_cntr := pixel_cntr + 1;
+ fifo_rd <= '1';
+ shift_reg := sl(shift_reg,8);
+ else
+ -- Simple increment
+ pixel_cntr := pixel_cntr + 1;
+ fifo_rd <= '0';
+ shift_reg := sl(shift_reg,8);
+ end if;
+ end if;
+ when others => -- Unsupported setting. Do nothing
+ i_video_out(7 downto 0) <= (others => '0');
+ fifo_rd <= '0';
+ pixel_cntr := 0;
+ end case;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ video_out <= i_video_out;
+
+ -- Simple logic generates the high_prior output
+ priority: process is
+ begin
+ wait on video_fifo_usedw,fifo_treshold,video_fifo_full;
+ if (video_fifo_usedw < fifo_treshold and video_fifo_full = '0') then
+ high_prior <= '1';
+ else
+ high_prior <= '0';
+ end if;
+ end process;
+end mem_reader;
Index: wb_vga/tags/a01/vga_chip.vhd
===================================================================
--- wb_vga/tags/a01/vga_chip.vhd (nonexistent)
+++ wb_vga/tags/a01/vga_chip.vhd (revision 8)
@@ -0,0 +1,152 @@
+--
+-- File: vga_chip.vhd
+--
+-- (c) Copyright Andras Tantos 2001/03/31
+-- This code is distributed under the terms and conditions of the GNU General Public Lince.
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+-- same as VGA_CORE but without generics. Suited for post-layout simulation.
+entity vga_chip is
+ port (
+ clk_i: in std_logic;
+ clk_en: in std_logic := '1';
+ rst_i: in std_logic := '0';
+
+ -- CPU bus interface
+ dat_i: in std_logic_vector (8-1 downto 0);
+ dat_oi: in std_logic_vector (8-1 downto 0);
+ dat_o: out std_logic_vector (8-1 downto 0);
+ cyc_i: in std_logic;
+ ack_o: out std_logic;
+ ack_oi: in std_logic;
+ we_i: in std_logic;
+ vmem_stb_i: in std_logic;
+ reg_stb_i: in std_logic;
+ adr_i: in std_logic_vector (20 downto 0);
+
+ -- video memory SRAM interface
+ s_data : inout std_logic_vector((16-1) downto 0);
+ s_addr : out std_logic_vector((20-1) downto 0);
+ s_oen : out std_logic;
+ s_wrhn : out std_logic;
+ s_wrln : out std_logic;
+ s_cen : out std_logic;
+
+ -- sync blank and video signal outputs
+ h_sync: out std_logic;
+ h_blank: out std_logic;
+ v_sync: out std_logic;
+ v_blank: out std_logic;
+ h_tc: out std_logic;
+ v_tc: out std_logic;
+ blank: out std_logic;
+ video_out: out std_logic_vector (7 downto 0); -- video output binary signal (unused bits are forced to 0)
+
+ -- TEST SIGNALS
+ T_v_we_o: out std_logic;
+ T_v_stb_o: out std_logic;
+ T_v_ack_i: out std_logic;
+ T_v_adr_o : out std_logic_vector((20-1) downto 0);
+ T_v_sel_o : out std_logic_vector((16/8)-1 downto 0);
+ T_v_dat_o : out std_logic_vector((16-1) downto 0);
+ T_v_dat_i : out std_logic_vector((16-1) downto 0)
+ );
+end vga_chip;
+
+architecture vga_chip of vga_chip is
+ component vga_core
+ generic (
+ -- cannot be overwritten at the moment...
+ v_mem_width: positive := 16;
+ fifo_size: positive := 256;
+ v_addr_width : positive := 20;
+ bus_width: positive := 8
+ );
+ port (
+ clk_i: in std_logic;
+ clk_en: in std_logic := '1';
+ rst_i: in std_logic := '0';
+
+ -- CPU bus interface
+ dat_i: in std_logic_vector (bus_width-1 downto 0);
+ dat_oi: in std_logic_vector (bus_width-1 downto 0);
+ dat_o: out std_logic_vector (bus_width-1 downto 0);
+ cyc_i: in std_logic;
+ ack_o: out std_logic;
+ ack_oi: in std_logic;
+ we_i: in std_logic;
+ vmem_stb_i: in std_logic;
+ reg_stb_i: in std_logic;
+ adr_i: in std_logic_vector (v_addr_width downto 0);
+
+ -- video memory SRAM interface
+ s_data : inout std_logic_vector((v_mem_width-1) downto 0);
+ s_addr : out std_logic_vector((v_addr_width-1) downto 0);
+ s_oen : out std_logic;
+ s_wrhn : out std_logic;
+ s_wrln : out std_logic;
+ s_cen : out std_logic;
+
+ -- sync blank and video signal outputs
+ h_sync: out std_logic;
+ h_blank: out std_logic;
+ v_sync: out std_logic;
+ v_blank: out std_logic;
+ h_tc: out std_logic;
+ v_tc: out std_logic;
+ blank: out std_logic;
+ video_out: out std_logic_vector (7 downto 0); -- video output binary signal (unused bits are forced to 0)
+
+ -- TEST SIGNALS
+ T_v_we_o: out std_logic;
+ T_v_stb_o: out std_logic;
+ T_v_ack_i: out std_logic;
+ T_v_adr_o : out std_logic_vector((v_addr_width-1) downto 0);
+ T_v_sel_o : out std_logic_vector((v_addr_width/8)-1 downto 0);
+ T_v_dat_o : out std_logic_vector((v_mem_width-1) downto 0);
+ T_v_dat_i : out std_logic_vector((v_mem_width-1) downto 0)
+ );
+ end component;
+begin
+ Core : vga_core
+ port map (
+ clk_i => clk_i,
+ clk_en => clk_en,
+ rst_i => rst_i,
+ dat_i => dat_i,
+ dat_oi => dat_oi,
+ dat_o => dat_o,
+ cyc_i => cyc_i,
+ ack_o => ack_o,
+ ack_oi => ack_oi,
+ we_i => we_i,
+ vmem_stb_i => vmem_stb_i,
+ reg_stb_i => reg_stb_i,
+ adr_i => adr_i,
+ s_data => s_data,
+ s_addr => s_addr,
+ s_oen => s_oen,
+ s_wrhn => s_wrhn,
+ s_wrln => s_wrln,
+ s_cen => s_cen,
+ h_sync => h_sync,
+ h_blank => h_blank,
+ v_sync => v_sync,
+ v_blank => v_blank,
+ h_tc => h_tc,
+ v_tc => v_tc,
+ blank => blank,
+ video_out => video_out,
+
+ T_v_we_o => T_v_we_o,
+ T_v_stb_o => T_v_stb_o,
+ T_v_ack_i => T_v_ack_i,
+ T_v_adr_o => T_v_adr_o,
+ T_v_sel_o => T_v_sel_o,
+ T_v_dat_o => T_v_dat_o,
+ T_v_dat_i => T_v_dat_i
+ );
+end vga_chip;
Index: wb_vga/tags/a01/sync_gen.vhd
===================================================================
--- wb_vga/tags/a01/sync_gen.vhd (nonexistent)
+++ wb_vga/tags/a01/sync_gen.vhd (revision 8)
@@ -0,0 +1,80 @@
+--
+-- Programmable sync generator.
+--
+-- (c) Copyright Andras Tantos 2001/03/31
+-- This code is distributed under the terms and conditions of the GNU General Public Lince.
+--
+
+-- Standard library.
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.technology.all;
+
+entity sync_gen is
+ port (
+ clk: in std_logic;
+ clk_en: in std_logic;
+ reset: in std_logic := '0';
+
+ bs: in std_logic_vector(7 downto 0);
+ ss: in std_logic_vector(7 downto 0);
+ se: in std_logic_vector(7 downto 0);
+ total: in std_logic_vector(7 downto 0);
+
+ sync: out std_logic;
+ blank: out std_logic;
+ tc: out std_logic;
+
+ count: out std_logic_vector (7 downto 0)
+ );
+end sync_gen;
+
+architecture sync_gen of sync_gen is
+begin
+ -- And the sequential machine generating the output signals.
+ generator: process is
+ variable state: std_logic_vector(7 downto 0);
+ begin
+ wait until clk'event and clk='1';
+ if (reset = '1') then
+ tc <= '0';
+ state := (others => '0');
+ sync <= '0';
+ tc <= '0';
+ blank <= '1';
+ else
+ if (clk_en='1') then
+ if (state = bs) then
+ sync <= '0';
+ blank <= '1';
+ tc <= '0';
+ state := add_one(state);
+ elsif (state = ss) then
+ sync <= '1';
+ blank <= '1';
+ tc <= '1';
+ state := add_one(state);
+ elsif (state = se) then
+ sync <= '0';
+ blank <= '1';
+ tc <= '0';
+ state := add_one(state);
+ elsif (state = total) then
+ sync <= '0';
+ blank <= '0';
+ tc <= '0';
+ state := (others => '0');
+ else
+ tc <= '0';
+ state := add_one(state);
+ end if;
+ count <= state;
+ else
+ tc <= '0';
+ end if;
+ end if;
+ end process;
+end sync_gen;
Index: wb_vga/tags/a01/vga_core.vhd
===================================================================
--- wb_vga/tags/a01/vga_core.vhd (nonexistent)
+++ wb_vga/tags/a01/vga_core.vhd (revision 8)
@@ -0,0 +1,774 @@
+--
+-- File: vga_core.vhd
+--
+-- (c) Copyright Andras Tantos 2001/03/31
+-- This code is distributed under the terms and conditions of the GNU General Public Lince.
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library work;
+--use wb_tk.all;
+use work.wb_tk.all;
+
+entity vga_core is
+ generic (
+ -- cannot be overwritten at the moment...
+ v_mem_width: positive := 16;
+ fifo_size: positive := 256;
+ v_addr_width : positive := 20;
+ bus_width: positive := 8
+ );
+ port (
+ clk_i: in std_logic;
+ clk_en: in std_logic := '1';
+ rst_i: in std_logic := '0';
+
+ -- CPU bus interface
+ dat_i: in std_logic_vector (bus_width-1 downto 0);
+ dat_oi: in std_logic_vector (bus_width-1 downto 0);
+ dat_o: out std_logic_vector (bus_width-1 downto 0);
+ cyc_i: in std_logic;
+ ack_o: out std_logic;
+ ack_oi: in std_logic;
+ we_i: in std_logic;
+ vmem_stb_i: in std_logic;
+ reg_stb_i: in std_logic;
+ adr_i: in std_logic_vector (v_addr_width downto 0);
+
+ -- video memory SRAM interface
+ s_data : inout std_logic_vector((v_mem_width-1) downto 0);
+ s_addr : out std_logic_vector((v_addr_width-1) downto 0);
+ s_oen : out std_logic;
+ s_wrhn : out std_logic;
+ s_wrln : out std_logic;
+ s_cen : out std_logic;
+
+ -- sync blank and video signal outputs
+ h_sync: out std_logic;
+ h_blank: out std_logic;
+ v_sync: out std_logic;
+ v_blank: out std_logic;
+ h_tc: out std_logic;
+ v_tc: out std_logic;
+ blank: out std_logic;
+ video_out: out std_logic_vector (7 downto 0); -- video output binary signal (unused bits are forced to 0)
+
+ -- TEST SIGNALS
+ T_v_we_o: out std_logic;
+ T_v_stb_o: out std_logic;
+ T_v_ack_i: out std_logic;
+ T_v_adr_o : out std_logic_vector((v_addr_width-1) downto 0);
+ T_v_sel_o : out std_logic_vector((v_addr_width/8)-1 downto 0);
+ T_v_dat_o : out std_logic_vector((v_mem_width-1) downto 0);
+ T_v_dat_i : out std_logic_vector((v_mem_width-1) downto 0)
+ );
+end vga_core;
+
+architecture vga_core of vga_core is
+ component video_engine
+ generic (
+ v_mem_width: positive := 16;
+ v_addr_width: positive:= 20;
+ fifo_size: positive := 256;
+ dual_scan_fifo_size: positive := 256
+ );
+ port (
+ clk: in std_logic;
+ clk_en: in std_logic := '1';
+ reset: in std_logic := '0';
+
+ total: in std_logic_vector(v_addr_width-1 downto 0); -- total video memory size in bytes 7..0
+ fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold
+ bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8
+ multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans
+
+ hbs: in std_logic_vector(7 downto 0);
+ hss: in std_logic_vector(7 downto 0);
+ hse: in std_logic_vector(7 downto 0);
+ htotal: in std_logic_vector(7 downto 0);
+ vbs: in std_logic_vector(7 downto 0);
+ vss: in std_logic_vector(7 downto 0);
+ vse: in std_logic_vector(7 downto 0);
+ vtotal: in std_logic_vector(7 downto 0);
+
+ pps: in std_logic_vector(7 downto 0);
+
+ high_prior: out std_logic; -- signals to the memory arbitrer to give high
+ -- priority to the video engine
+ v_mem_rd: out std_logic; -- video memory read request
+ v_mem_rdy: in std_logic; -- video memory data ready
+ v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address
+ v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data
+
+ h_sync: out std_logic;
+ h_blank: out std_logic;
+ v_sync: out std_logic;
+ v_blank: out std_logic;
+ h_tc: out std_logic;
+ v_tc: out std_logic;
+ blank: out std_logic;
+ video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
+ );
+ end component video_engine;
+
+ component wb_async_slave
+ generic (
+ width: positive := 16;
+ addr_width: positive := 20
+ );
+ port (
+ clk_i: in std_logic;
+ rst_i: in std_logic := '0';
+
+ -- interface for wait-state generator state-machine
+ wait_state: in std_logic_vector (3 downto 0);
+
+ -- interface to wishbone master device
+ adr_i: in std_logic_vector (addr_width-1 downto 0);
+ sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
+ dat_i: in std_logic_vector (width-1 downto 0);
+ dat_o: out std_logic_vector (width-1 downto 0);
+ dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
+ we_i: in std_logic;
+ stb_i: in std_logic;
+ ack_o: out std_logic := '0';
+ ack_oi: in std_logic := '-';
+
+ -- interface to async slave
+ a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
+ a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
+ a_rdn: out std_logic := '1';
+ a_wrn: out std_logic := '1';
+ a_cen: out std_logic := '1';
+ -- byte-enable signals
+ a_byen: out std_logic_vector ((addr_width/8)-1 downto 0)
+ );
+ end component;
+
+ component wb_arbiter
+ port (
+-- clk: in std_logic;
+ rst_i: in std_logic := '0';
+
+ -- interface to master device a
+ a_we_i: in std_logic;
+ a_stb_i: in std_logic;
+ a_cyc_i: in std_logic;
+ a_ack_o: out std_logic;
+ a_ack_oi: in std_logic := '-';
+ a_err_o: out std_logic;
+ a_err_oi: in std_logic := '-';
+ a_rty_o: out std_logic;
+ a_rty_oi: in std_logic := '-';
+
+ -- interface to master device b
+ b_we_i: in std_logic;
+ b_stb_i: in std_logic;
+ b_cyc_i: in std_logic;
+ b_ack_o: out std_logic;
+ b_ack_oi: in std_logic := '-';
+ b_err_o: out std_logic;
+ b_err_oi: in std_logic := '-';
+ b_rty_o: out std_logic;
+ b_rty_oi: in std_logic := '-';
+
+ -- interface to shared devices
+ s_we_o: out std_logic;
+ s_stb_o: out std_logic;
+ s_cyc_o: out std_logic;
+ s_ack_i: in std_logic;
+ s_err_i: in std_logic := '-';
+ s_rty_i: in std_logic := '-';
+
+ mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
+
+ -- misc control lines
+ priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
+ );
+ end component;
+
+ component wb_out_reg
+ generic (
+ width : positive := 8;
+ bus_width: positive := 8;
+ offset: integer := 0
+ );
+ port (
+ clk_i: in std_logic;
+ rst_i: in std_logic;
+ rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
+
+ dat_i: in std_logic_vector (bus_width-1 downto 0);
+ dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
+ dat_o: out std_logic_vector (bus_width-1 downto 0);
+ q: out std_logic_vector (width-1 downto 0);
+ we_i: in std_logic;
+ stb_i: in std_logic;
+ ack_o: out std_logic;
+ ack_oi: in std_logic := '-'
+ );
+ end component;
+
+ component wb_bus_upsize
+ generic (
+ m_bus_width: positive := 8; -- master bus width
+ m_addr_width: positive := 21; -- master bus width
+ s_bus_width: positive := 16; -- slave bus width
+ little_endien: boolean := true -- if set to false, big endien
+ );
+ port (
+-- clk_i: in std_logic;
+-- rst_i: in std_logic := '0';
+
+ -- Master bus interface
+ m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);
+ m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');
+ m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);
+ m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');
+ m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);
+ m_cyc_i: in std_logic;
+ m_ack_o: out std_logic;
+ m_ack_oi: in std_logic := '-';
+ m_err_o: out std_logic;
+ m_err_oi: in std_logic := '-';
+ m_rty_o: out std_logic;
+ m_rty_oi: in std_logic := '-';
+ m_we_i: in std_logic;
+ m_stb_i: in std_logic;
+
+ -- Slave bus interface
+ s_adr_o: out std_logic_vector (m_addr_width-2 downto 0);
+ s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
+ s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
+ s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
+ s_cyc_o: out std_logic;
+ s_ack_i: in std_logic;
+ s_err_i: in std_logic := '-';
+ s_rty_i: in std_logic := '-';
+ s_we_o: out std_logic;
+ s_stb_o: out std_logic
+ );
+ end component;
+
+ signal reset_core: std_logic_vector(0 downto 0);
+ signal total: std_logic_vector(v_addr_width-1 downto 0);
+ signal fifo_treshold: std_logic_vector(7 downto 0);
+ signal bpp: std_logic_vector(1 downto 0);
+ signal multi_scan: std_logic_vector(1 downto 0);
+ signal hbs: std_logic_vector(7 downto 0);
+ signal hss: std_logic_vector(7 downto 0);
+ signal hse: std_logic_vector(7 downto 0);
+ signal htotal: std_logic_vector(7 downto 0);
+ signal vbs: std_logic_vector(7 downto 0);
+ signal vss: std_logic_vector(7 downto 0);
+ signal vse: std_logic_vector(7 downto 0);
+ signal vtotal: std_logic_vector(7 downto 0);
+ signal pps: std_logic_vector(7 downto 0);
+ signal wait_state: std_logic_vector (3 downto 0);
+ signal sync_pol: std_logic_vector (3 downto 0);
+
+ signal reset_core_do: std_logic_vector(bus_width-1 downto 0);
+ signal total0_do: std_logic_vector(bus_width-1 downto 0);
+ signal total1_do: std_logic_vector(bus_width-1 downto 0);
+ signal total2_do: std_logic_vector(bus_width-1 downto 0);
+ signal fifo_treshold_do: std_logic_vector(bus_width-1 downto 0);
+ signal bpp_do: std_logic_vector(bus_width-1 downto 0);
+ signal multi_scan_do: std_logic_vector(bus_width-1 downto 0);
+ signal hbs_do: std_logic_vector(bus_width-1 downto 0);
+ signal hss_do: std_logic_vector(bus_width-1 downto 0);
+ signal hse_do: std_logic_vector(bus_width-1 downto 0);
+ signal htotal_do: std_logic_vector(bus_width-1 downto 0);
+ signal vbs_do: std_logic_vector(bus_width-1 downto 0);
+ signal vss_do: std_logic_vector(bus_width-1 downto 0);
+ signal vse_do: std_logic_vector(bus_width-1 downto 0);
+ signal vtotal_do: std_logic_vector(bus_width-1 downto 0);
+ signal pps_do: std_logic_vector(bus_width-1 downto 0);
+ signal wait_state_do: std_logic_vector(bus_width-1 downto 0);
+ signal vm_do: std_logic_vector(bus_width-1 downto 0);
+
+ signal reset_core_sel: std_logic;
+ signal total0_sel: std_logic;
+ signal total1_sel: std_logic;
+ signal total2_sel: std_logic;
+ signal fifo_treshold_sel: std_logic;
+ signal bpp_sel: std_logic;
+ signal multi_scan_sel: std_logic;
+ signal hbs_sel: std_logic;
+ signal hss_sel: std_logic;
+ signal hse_sel: std_logic;
+ signal htotal_sel: std_logic;
+ signal vbs_sel: std_logic;
+ signal vss_sel: std_logic;
+ signal vse_sel: std_logic;
+ signal vtotal_sel: std_logic;
+ signal pps_sel: std_logic;
+ signal wait_state_sel: std_logic;
+ signal sync_pol_sel: std_logic;
+
+ signal reset_core_ack: std_logic;
+ signal total0_ack: std_logic;
+ signal total1_ack: std_logic;
+ signal total2_ack: std_logic;
+ signal fifo_treshold_ack: std_logic;
+ signal bpp_ack: std_logic;
+ signal multi_scan_ack: std_logic;
+ signal hbs_ack: std_logic;
+ signal hss_ack: std_logic;
+ signal hse_ack: std_logic;
+ signal htotal_ack: std_logic;
+ signal vbs_ack: std_logic;
+ signal vss_ack: std_logic;
+ signal vse_ack: std_logic;
+ signal vtotal_ack: std_logic;
+ signal pps_ack: std_logic;
+ signal wait_state_ack: std_logic;
+ signal vm_ack: std_logic;
+
+ signal a_adr_o : std_logic_vector((v_addr_width-1) downto 0);
+ signal a_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0);
+ signal a_dat_o : std_logic_vector((v_mem_width-1) downto 0);
+ signal a_dat_i : std_logic_vector((v_mem_width-1) downto 0);
+ signal a_we_o : std_logic;
+ signal a_stb_o : std_logic;
+ signal a_cyc_o : std_logic;
+ signal a_ack_i : std_logic;
+
+ signal b_adr_o : std_logic_vector((v_addr_width-1) downto 0);
+ signal b_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0);
+-- signal b_dat_o : std_logic_vector((v_mem_width-1) downto 0);
+ signal b_dat_i : std_logic_vector((v_mem_width-1) downto 0);
+ signal b_stb_o : std_logic;
+-- signal b_we_o : std_logic;
+-- signal b_cyc_o : std_logic;
+ signal b_ack_i : std_logic;
+
+ signal v_we_o: std_logic;
+ signal v_stb_o: std_logic;
+ signal v_ack_i: std_logic;
+ signal v_adr_o : std_logic_vector((v_addr_width-1) downto 0);
+ signal v_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0);
+ signal v_dat_o : std_logic_vector((v_mem_width-1) downto 0);
+ signal v_dat_i : std_logic_vector((v_mem_width-1) downto 0);
+
+ signal s_byen : std_logic_vector((v_addr_width/8)-1 downto 0);
+
+ signal mux_signal: std_logic;
+
+ signal high_prior: std_logic;
+
+ signal reset_engine: std_logic;
+
+ signal i_h_sync: std_logic;
+ signal i_h_blank: std_logic;
+ signal i_v_sync: std_logic;
+ signal i_v_blank: std_logic;
+
+ signal s_wrn : std_logic;
+
+begin
+ -- map all registers:
+ reset_core_reg: wb_out_reg
+ generic map( width => 1, bus_width => bus_width , offset => 4 )
+ port map(
+ stb_i => reset_core_sel,
+ q => reset_core,
+ rst_val => "1",
+ dat_oi => vm_do,
+ dat_o => reset_core_do,
+ ack_oi => vm_ack,
+ ack_o => reset_core_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ total0_reg: wb_out_reg
+ generic map( width => 8, bus_width => bus_width , offset => 0 )
+ port map(
+ stb_i => total0_sel,
+ q => total(7 downto 0),
+ rst_val => "00000000",
+ dat_oi => reset_core_do,
+ dat_o => total0_do,
+ ack_oi => reset_core_ack,
+ ack_o => total0_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ total1_reg: wb_out_reg
+ generic map( width => 8, bus_width => bus_width , offset => 0 )
+ port map(
+ stb_i => total1_sel,
+ q => total(15 downto 8),
+ rst_val => "00000000",
+ dat_oi => total0_do,
+ dat_o => total1_do,
+ ack_oi => total0_ack,
+ ack_o => total1_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ total2_reg: wb_out_reg
+ generic map( width => 4, bus_width => bus_width , offset => 0 )
+ port map(
+ stb_i => total2_sel,
+ q => total(19 downto 16),
+ rst_val => "0000",
+ dat_oi => total1_do,
+ dat_o => total2_do,
+ ack_oi => total1_ack,
+ ack_o => total2_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ fifo_treshold_reg: wb_out_reg
+ generic map( width => 8, bus_width => bus_width , offset => 0 )
+ port map(
+ stb_i => fifo_treshold_sel,
+ q => fifo_treshold,
+ rst_val => "00000000",
+ dat_oi => total2_do,
+ dat_o => fifo_treshold_do,
+ ack_oi => total2_ack,
+ ack_o => fifo_treshold_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ bpp_reg: wb_out_reg
+ generic map( width => 2, bus_width => bus_width , offset => 0 )
+ port map(
+ stb_i => bpp_sel,
+ q => bpp,
+ rst_val => "00",
+ dat_oi => fifo_treshold_do,
+ dat_o => bpp_do,
+ ack_oi => fifo_treshold_ack,
+ ack_o => bpp_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ multi_scan_reg: wb_out_reg
+ generic map( width => 2, bus_width => bus_width , offset => 2 )
+ port map(
+ stb_i => multi_scan_sel,
+ q => multi_scan,
+ rst_val => "00",
+ dat_oi => bpp_do,
+ dat_o => multi_scan_do,
+ ack_oi => bpp_ack,
+ ack_o => multi_scan_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ hbs_reg: wb_out_reg
+ generic map( width => 8, bus_width => bus_width , offset => 0 )
+ port map(
+ stb_i => hbs_sel,
+ q => hbs,
+ rst_val => "00000000",
+ dat_oi => multi_scan_do,
+ dat_o => hbs_do,
+ ack_oi => multi_scan_ack,
+ ack_o => hbs_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ hss_reg: wb_out_reg
+ generic map( width => 8, bus_width => bus_width , offset => 0 )
+ port map(
+ stb_i => hss_sel,
+ q => hss,
+ rst_val => "00000000",
+ dat_oi => hbs_do,
+ dat_o => hss_do,
+ ack_oi => hbs_ack,
+ ack_o => hss_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ hse_reg: wb_out_reg
+ generic map( width => 8, bus_width => bus_width , offset => 0 )
+ port map(
+ stb_i => hse_sel,
+ q => hse,
+ rst_val => "00000000",
+ dat_oi => hss_do,
+ dat_o => hse_do,
+ ack_oi => hss_ack,
+ ack_o => hse_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ htotal_reg: wb_out_reg
+ generic map( width => 8, bus_width => bus_width , offset => 0 )
+ port map(
+ stb_i => htotal_sel,
+ q => htotal,
+ rst_val => "00000000",
+ dat_oi => hse_do,
+ dat_o => htotal_do,
+ ack_oi => hse_ack,
+ ack_o => htotal_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ vbs_reg: wb_out_reg
+ generic map( width => 8, bus_width => bus_width , offset => 0 )
+ port map(
+ stb_i => vbs_sel,
+ q => vbs,
+ rst_val => "00000000",
+ dat_oi => htotal_do,
+ dat_o => vbs_do,
+ ack_oi => htotal_ack,
+ ack_o => vbs_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ vss_reg: wb_out_reg
+ generic map( width => 8, bus_width => bus_width , offset => 0 )
+ port map(
+ stb_i => vss_sel,
+ q => vss,
+ rst_val => "00000000",
+ dat_oi => vbs_do,
+ dat_o => vss_do,
+ ack_oi => vbs_ack,
+ ack_o => vss_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ vse_reg: wb_out_reg
+ generic map( width => 8, bus_width => bus_width , offset => 0 )
+ port map(
+ stb_i => vse_sel,
+ q => vse,
+ rst_val => "00000000",
+ dat_oi => vss_do,
+ dat_o => vse_do,
+ ack_oi => vss_ack,
+ ack_o => vse_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ vtotal_reg: wb_out_reg
+ generic map( width => 8, bus_width => bus_width , offset => 0 )
+ port map(
+ stb_i => vtotal_sel,
+ q => vtotal,
+ rst_val => "00000000",
+ dat_oi => vse_do,
+ dat_o => vtotal_do,
+ ack_oi => vse_ack,
+ ack_o => vtotal_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ pps_reg: wb_out_reg
+ generic map( width => 8, bus_width => bus_width , offset => 0 )
+ port map(
+ stb_i => pps_sel,
+ q => pps,
+ rst_val => "00000000",
+ dat_oi => vtotal_do,
+ dat_o => pps_do,
+ ack_oi => vtotal_ack,
+ ack_o => pps_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ wait_state_reg: wb_out_reg
+ generic map( width => 4, bus_width => bus_width , offset => 0 )
+ port map(
+ stb_i => wait_state_sel,
+ q => wait_state,
+ rst_val => "0000",
+ dat_oi => pps_do,
+ dat_o => wait_state_do,
+ ack_oi => pps_ack,
+ ack_o => wait_state_ack,
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+ sync_pol_reg: wb_out_reg
+ generic map( width => 4, bus_width => bus_width , offset => 4 )
+ port map(
+ stb_i => sync_pol_sel,
+ q => sync_pol,
+ rst_val => "0000",
+ dat_oi => wait_state_do,
+ dat_o => dat_o, -- END OF THE CHAIN
+ ack_oi => wait_state_ack,
+ ack_o => ack_o, -- END OF THE CHAIN
+ we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
+
+ reset_engine <= rst_i or reset_core(0);
+
+ v_e: video_engine
+ generic map ( v_mem_width => v_mem_width, v_addr_width => v_addr_width, fifo_size => fifo_size, dual_scan_fifo_size => fifo_size )
+ port map (
+ clk => clk_i,
+ clk_en => clk_en,
+ reset => reset_engine,
+ total => total,
+ fifo_treshold => fifo_treshold,
+ bpp => bpp,
+ multi_scan => multi_scan,
+ hbs => hbs,
+ hss => hss,
+ hse => hse,
+ htotal => htotal,
+ vbs => vbs,
+ vss => vss,
+ vse => vse,
+ vtotal => vtotal,
+ pps => pps,
+
+ high_prior => high_prior,
+
+ v_mem_rd => b_stb_o,
+ v_mem_rdy => b_ack_i,
+ v_mem_addr => b_adr_o,
+ v_mem_data => b_dat_i,
+
+ h_sync => i_h_sync,
+ h_blank => i_h_blank,
+ v_sync => i_v_sync,
+ v_blank => i_v_blank,
+ h_tc => h_tc,
+ v_tc => v_tc,
+ blank => blank,
+ video_out => video_out
+ );
+
+ h_sync <= i_h_sync xor sync_pol(0);
+ v_sync <= i_v_sync xor sync_pol(1);
+ h_blank <= i_h_blank;-- xor sync_pol(2);
+ v_blank <= i_v_blank;-- xor sync_pol(3);
+
+ resize: wb_bus_upsize
+ generic map (
+ m_bus_width => bus_width, s_bus_width => v_mem_width, m_addr_width => v_addr_width+1
+ )
+ port map (
+ m_adr_i => adr_i,
+-- m_sel_i => (others => '1'),
+ m_dat_i => dat_i,
+ m_dat_oi => dat_oi, -- Beginning of the chain
+ m_cyc_i => cyc_i,
+ m_dat_o => vm_do,
+ m_ack_o => vm_ack,
+ m_ack_oi => ack_oi, -- Beginning of the chain
+ m_we_i => we_i,
+ m_stb_i => vmem_stb_i,
+
+ s_adr_o => a_adr_o,
+ s_sel_o => a_sel_o,
+ s_dat_i => a_dat_i,
+ s_dat_o => a_dat_o,
+ s_cyc_o => a_cyc_o,
+ s_ack_i => a_ack_i,
+ s_we_o => a_we_o,
+ s_stb_o => a_stb_o
+ );
+
+
+ arbiter: wb_arbiter
+ port map (
+ rst_i => reset_engine,
+
+ a_we_i => a_we_o,
+ a_cyc_i => a_cyc_o,
+ a_stb_i => a_stb_o,
+ a_ack_o => a_ack_i,
+ a_ack_oi => '-',
+
+ b_we_i => '0',
+ b_cyc_i => b_stb_o,
+ b_stb_i => b_stb_o,
+ b_ack_o => b_ack_i,
+ b_ack_oi => '0', -- maybe not needed at all
+
+ s_we_o => v_we_o,
+ s_stb_o => v_stb_o,
+ s_ack_i => v_ack_i,
+
+ mux_signal => mux_signal,
+
+ priority => high_prior
+ );
+
+ b_sel_o <= (others => '1');
+
+ bus_mux: process is
+ begin
+ wait on mux_signal, v_dat_i, a_adr_o, a_dat_o, b_adr_o, a_sel_o, b_sel_o;
+ if (mux_signal = '0') then
+ v_adr_o <= a_adr_o;
+ v_sel_o <= a_sel_o;
+ v_dat_o <= a_dat_o;
+ a_dat_i <= v_dat_i;
+ b_dat_i <= (others => '-');
+ else
+ v_adr_o <= b_adr_o;
+ v_sel_o <= b_sel_o;
+ v_dat_o <= (others => '-');
+ b_dat_i <= v_dat_i;
+ a_dat_i <= (others => '-');
+ end if;
+ end process;
+
+ mem_driver: wb_async_slave
+ generic map (width => v_mem_width, addr_width => v_addr_width)
+ port map (
+ clk_i => clk_i,
+ rst_i => reset_engine,
+
+ wait_state => wait_state,
+
+ adr_i => v_adr_o,
+ sel_i => v_sel_o,
+ dat_o => v_dat_i,
+ dat_i => v_dat_o,
+-- dat_oi => (others => '0'), -- may not be needed
+ we_i => v_we_o,
+ stb_i => v_stb_o,
+ ack_o => v_ack_i,
+ ack_oi => '0', -- may not be needed
+
+ a_data => s_data,
+ a_addr => s_addr,
+ a_rdn => s_oen,
+ a_wrn => s_wrn,
+ a_cen => s_cen,
+ a_byen => s_byen
+ );
+
+ s_wrln <= s_wrn or s_byen(0);
+ s_wrhn <= s_wrn or s_byen(1);
+
+ addr_decoder: process is
+ begin
+ wait on reg_stb_i, adr_i;
+
+ reset_core_sel <= '0';
+ total0_sel <= '0';
+ total1_sel <= '0';
+ total2_sel <= '0';
+ fifo_treshold_sel <= '0';
+ bpp_sel <= '0';
+ multi_scan_sel <= '0';
+ hbs_sel <= '0';
+ hss_sel <= '0';
+ hse_sel <= '0';
+ htotal_sel <= '0';
+ vbs_sel <= '0';
+ vss_sel <= '0';
+ vse_sel <= '0';
+ vtotal_sel <= '0';
+ pps_sel <= '0';
+ wait_state_sel <= '0';
+ sync_pol_sel <= '0';
+
+ if (reg_stb_i = '1') then
+ case (adr_i(4 downto 0)) is
+ when "00000" => total0_sel <= '1';
+ when "00001" => total1_sel <= '1';
+ when "00010" => total2_sel <= '1';
+ when "00011" => fifo_treshold_sel <= '1';
+
+ when "00100" => hbs_sel <= '1';
+ when "00101" => hss_sel <= '1';
+ when "00110" => hse_sel <= '1';
+ when "00111" => htotal_sel <= '1';
+
+ when "01000" => vbs_sel <= '1';
+ when "01001" => vss_sel <= '1';
+ when "01010" => vse_sel <= '1';
+ when "01011" => vtotal_sel <= '1';
+
+ when "01100" => pps_sel <= '1';
+ when "01101" => wait_state_sel <= '1'; sync_pol_sel <= '1';
+ when "01110" => bpp_sel <= '1'; multi_scan_sel <= '1'; reset_core_sel <= '1';
+ when others =>
+ end case;
+ end if;
+ end process;
+
+ -- TEST SIGNALS
+ T_v_we_o <= v_we_o;
+ T_v_stb_o <= v_stb_o;
+ T_v_ack_i <= v_ack_i;
+ T_v_adr_o <= v_adr_o;
+ T_v_sel_o <= v_sel_o;
+ T_v_dat_o <= v_dat_o;
+ T_v_dat_i <= v_dat_i;
+
+end vga_core;
+
Index: wb_vga/tags/a01/wb_tk.vhd
===================================================================
--- wb_vga/tags/a01/wb_tk.vhd (nonexistent)
+++ wb_vga/tags/a01/wb_tk.vhd (revision 8)
@@ -0,0 +1,914 @@
+--
+-- Wishbone bus toolkit.
+--
+-- (c) Copyright Andras Tantos 2001/03/31
+-- This code is distributed under the terms and conditions of the GNU General Public Lince.
+--
+--
+-- ELEMENTS:
+-- wb_bus_upsize: bus upsizer. Currently only 8->16 bit bus resize is supported
+-- wb_async_slave: Wishbone bus to async (SRAM-like) bus slave bridge.
+-- wb_arbiter: two-way bus arbiter. Asyncronous logic ensures 0-ws operation on shared bus
+-- wb_out_reg: Wishbone bus compatible output register.
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package wb_tk is
+ component wb_bus_upsize is
+ generic (
+ m_bus_width: positive := 8; -- master bus width
+ m_addr_width: positive := 21; -- master bus width
+ s_bus_width: positive := 16; -- slave bus width
+ s_addr_width: positive := 20; -- master bus width
+ little_endien: boolean := true -- if set to false, big endien
+ );
+ port (
+ -- clk_i: in std_logic;
+ -- rst_i: in std_logic := '0';
+
+ -- Master bus interface
+ m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);
+ m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');
+ m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);
+ m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');
+ m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);
+ m_cyc_i: in std_logic;
+ m_ack_o: out std_logic;
+ m_ack_oi: in std_logic := '-';
+ m_err_o: out std_logic;
+ m_err_oi: in std_logic := '-';
+ m_rty_o: out std_logic;
+ m_rty_oi: in std_logic := '-';
+ m_we_i: in std_logic;
+ m_stb_i: in std_logic;
+
+ -- Slave bus interface
+ s_adr_o: out std_logic_vector (s_addr_width-1 downto 0);
+ s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
+ s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
+ s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
+ s_cyc_o: out std_logic;
+ s_ack_i: in std_logic;
+ s_err_i: in std_logic := '-';
+ s_rty_i: in std_logic := '-';
+ s_we_o: out std_logic;
+ s_stb_o: out std_logic
+ );
+ end component;
+
+ component wb_async_master is
+ generic (
+ width: positive := 16;
+ addr_width: positive := 20
+ );
+ port (
+ clk_i: in std_logic;
+ rst_i: in std_logic := '0';
+
+ -- interface to wb slave devices
+ s_adr_o: out std_logic_vector (addr_width-1 downto 0);
+ s_sel_o: out std_logic_vector ((width/8)-1 downto 0);
+ s_dat_i: in std_logic_vector (width-1 downto 0);
+ s_dat_o: out std_logic_vector (width-1 downto 0);
+ s_cyc_o: out std_logic;
+ s_ack_i: in std_logic;
+ s_err_i: in std_logic := '-';
+ s_rty_i: in std_logic := '-';
+ s_we_o: out std_logic;
+ s_stb_o: out std_logic;
+
+ -- interface to asyncron master device
+ a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
+ a_addr: in std_logic_vector (addr_width-1 downto 0) := (others => 'U');
+ a_rdn: in std_logic := '1';
+ a_wrn: in std_logic := '1';
+ a_cen: in std_logic := '1';
+ a_byen: in std_logic_vector ((width/8)-1 downto 0);
+ a_waitn: out std_logic
+ );
+ end component;
+
+ component wb_async_slave is
+ generic (
+ width: positive := 16;
+ addr_width: positive := 20
+ );
+ port (
+ clk_i: in std_logic;
+ rst_i: in std_logic := '0';
+
+ -- interface for wait-state generator state-machine
+ wait_state: in std_logic_vector (3 downto 0);
+
+ -- interface to wishbone master device
+ adr_i: in std_logic_vector (addr_width-1 downto 0);
+ sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
+ dat_i: in std_logic_vector (width-1 downto 0);
+ dat_o: out std_logic_vector (width-1 downto 0);
+ dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
+ we_i: in std_logic;
+ stb_i: in std_logic;
+ ack_o: out std_logic := '0';
+ ack_oi: in std_logic := '-';
+
+ -- interface to async slave
+ a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
+ a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
+ a_rdn: out std_logic := '1';
+ a_wrn: out std_logic := '1';
+ a_cen: out std_logic := '1';
+ -- byte-enable signals
+ a_byen: out std_logic_vector ((width/8)-1 downto 0)
+ );
+ end component;
+
+ component wb_arbiter is
+ port (
+ -- clk_i: in std_logic;
+ rst_i: in std_logic := '0';
+
+ -- interface to master device a
+ a_we_i: in std_logic;
+ a_stb_i: in std_logic;
+ a_cyc_i: in std_logic;
+ a_ack_o: out std_logic;
+ a_ack_oi: in std_logic := '-';
+ a_err_o: out std_logic;
+ a_err_oi: in std_logic := '-';
+ a_rty_o: out std_logic;
+ a_rty_oi: in std_logic := '-';
+
+ -- interface to master device b
+ b_we_i: in std_logic;
+ b_stb_i: in std_logic;
+ b_cyc_i: in std_logic;
+ b_ack_o: out std_logic;
+ b_ack_oi: in std_logic := '-';
+ b_err_o: out std_logic;
+ b_err_oi: in std_logic := '-';
+ b_rty_o: out std_logic;
+ b_rty_oi: in std_logic := '-';
+
+ -- interface to shared devices
+ s_we_o: out std_logic;
+ s_stb_o: out std_logic;
+ s_cyc_o: out std_logic;
+ s_ack_i: in std_logic;
+ s_err_i: in std_logic := '-';
+ s_rty_i: in std_logic := '-';
+
+ mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
+
+ -- misc control lines
+ priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
+ );
+ end component;
+
+ component wb_out_reg is
+ generic (
+ width : positive := 8;
+ bus_width: positive := 8;
+ offset: integer := 0
+ );
+ port (
+ clk_i: in std_logic;
+ rst_i: in std_logic;
+ rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
+
+ dat_i: in std_logic_vector (bus_width-1 downto 0);
+ dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
+ dat_o: out std_logic_vector (bus_width-1 downto 0);
+ q: out std_logic_vector (width-1 downto 0);
+ we_i: in std_logic;
+ stb_i: in std_logic;
+ ack_o: out std_logic;
+ ack_oi: in std_logic := '-'
+ );
+ end component;
+end wb_tk;
+
+-------------------------------------------------------------------------------
+--
+-- wb_bus_upsize
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+library synopsys;
+use IEEE.std_logic_1164.all;
+use synopsys.std_logic_arith.all;
+
+library work;
+use work.technology.all;
+
+entity wb_bus_upsize is
+ generic (
+ m_bus_width: positive := 8; -- master bus width
+ m_addr_width: positive := 21; -- master bus width
+ s_bus_width: positive := 16; -- slave bus width
+ s_addr_width: positive := 20; -- master bus width
+ little_endien: boolean := true -- if set to false, big endien
+ );
+ port (
+-- clk_i: in std_logic;
+-- rst_i: in std_logic := '0';
+
+ -- Master bus interface
+ m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);
+ m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');
+ m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);
+ m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');
+ m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);
+ m_cyc_i: in std_logic;
+ m_ack_o: out std_logic;
+ m_ack_oi: in std_logic := '-';
+ m_err_o: out std_logic;
+ m_err_oi: in std_logic := '-';
+ m_rty_o: out std_logic;
+ m_rty_oi: in std_logic := '-';
+ m_we_i: in std_logic;
+ m_stb_i: in std_logic;
+
+ -- Slave bus interface
+ s_adr_o: out std_logic_vector (s_addr_width-1 downto 0);
+ s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
+ s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
+ s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
+ s_cyc_o: out std_logic;
+ s_ack_i: in std_logic;
+ s_err_i: in std_logic := '-';
+ s_rty_i: in std_logic := '-';
+ s_we_o: out std_logic;
+ s_stb_o: out std_logic
+ );
+end wb_bus_upsize;
+
+architecture wb_bus_upsize of wb_bus_upsize is
+ function log2(inp : integer) return integer is
+ begin
+ if (inp < 1) then return 0; end if;
+ if (inp < 2) then return 0; end if;
+ if (inp < 4) then return 1; end if;
+ if (inp < 8) then return 2; end if;
+ if (inp < 16) then return 3; end if;
+ if (inp < 32) then return 4; end if;
+ if (inp < 64) then return 5; end if;
+ if (inp < 128) then return 6; end if;
+ if (inp < 256) then return 7; end if;
+ if (inp < 512) then return 8; end if;
+ if (inp < 1024) then return 9; end if;
+ if (inp < 2048) then return 10; end if;
+ if (inp < 4096) then return 11; end if;
+ if (inp < 8192) then return 12; end if;
+ if (inp < 16384) then return 13; end if;
+ if (inp < 32768) then return 14; end if;
+ if (inp < 65538) then return 15; end if;
+ return 16;
+ end;
+ function equ(a : std_logic_vector; b : integer) return boolean is
+ variable b_s : std_logic_vector(a'RANGE);
+ begin
+ b_s := CONV_STD_LOGIC_VECTOR(b,a'HIGH+1);
+ return (a = b_s);
+ end;
+ constant addr_diff: integer := log2(s_bus_width/m_bus_width);
+ signal i_m_dat_o: std_logic_vector(m_bus_width-1 downto 0);
+begin
+ assert (m_addr_width = s_addr_width+addr_diff) report "Address widths are not consistent" severity FAILURE;
+ s_adr_o <= m_adr_i(m_addr_width-addr_diff downto addr_diff);
+ s_we_o <= m_we_i;
+ m_ack_o <= (m_stb_i and s_ack_i) or (not m_stb_i and m_ack_oi);
+ m_err_o <= (m_stb_i and s_err_i) or (not m_stb_i and m_err_oi);
+ m_rty_o <= (m_stb_i and s_rty_i) or (not m_stb_i and m_rty_oi);
+ s_stb_o <= m_stb_i;
+ s_cyc_o <= m_cyc_i;
+
+
+ sel_dat_mux: process is
+ begin
+ wait on s_dat_i, m_adr_i;
+ if (little_endien) then
+ for i in s_sel_o'RANGE loop
+ if (equ(m_adr_i(addr_diff-1 downto 0),i)) then
+ s_sel_o(i) <= '1';
+ i_m_dat_o <= s_dat_i(8*i+7 downto 8*i+0);
+ else
+ s_sel_o(i) <= '0';
+ end if;
+ end loop;
+ else
+ for i in s_sel_o'RANGE loop
+ if (equ(m_adr_i(addr_diff-1 downto 0),i)) then
+ s_sel_o(s_sel_o'HIGH-i) <= '1';
+ i_m_dat_o <= s_dat_i(s_dat_i'HIGH-8*i downto s_dat_i'HIGH-8*i-7);
+ else
+ s_sel_o(s_sel_o'HIGH-i) <= '0';
+ end if;
+ end loop;
+ end if;
+ end process;
+
+ d_i_for: for i in m_dat_o'RANGE generate
+ m_dat_o(i) <= (m_stb_i and i_m_dat_o(i)) or (not m_stb_i and m_dat_oi(i));
+ end generate;
+
+ d_o_for: for i in s_sel_o'RANGE generate
+ s_dat_o(8*i+7 downto 8*i+0) <= m_dat_i;
+ end generate;
+end wb_bus_upsize;
+
+-------------------------------------------------------------------------------
+--
+-- wb_async_master
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library work;
+use work.technology.all;
+
+entity wb_async_master is
+ generic (
+ width: positive := 16;
+ addr_width: positive := 20
+ );
+ port (
+ clk_i: in std_logic;
+ rst_i: in std_logic := '0';
+
+ -- interface to wb slave devices
+ s_adr_o: out std_logic_vector (addr_width-1 downto 0);
+ s_sel_o: out std_logic_vector ((width/8)-1 downto 0);
+ s_dat_i: in std_logic_vector (width-1 downto 0);
+ s_dat_o: out std_logic_vector (width-1 downto 0);
+ s_cyc_o: out std_logic;
+ s_ack_i: in std_logic;
+ s_err_i: in std_logic := '-';
+ s_rty_i: in std_logic := '-';
+ s_we_o: out std_logic;
+ s_stb_o: out std_logic;
+
+ -- interface to asyncron master device
+ a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
+ a_addr: in std_logic_vector (addr_width-1 downto 0) := (others => 'U');
+ a_rdn: in std_logic := '1';
+ a_wrn: in std_logic := '1';
+ a_cen: in std_logic := '1';
+ a_byen: in std_logic_vector ((width/8)-1 downto 0);
+ a_waitn: out std_logic
+ );
+end wb_async_master;
+
+architecture wb_async_master of wb_async_master is
+ component d_ff
+ port ( d : in STD_LOGIC;
+ clk: in STD_LOGIC;
+ ena: in STD_LOGIC := '1';
+ clr: in STD_LOGIC := '0';
+ pre: in STD_LOGIC := '0';
+ q : out STD_LOGIC
+ );
+ end component;
+ signal wg_clk, wg_pre, wg_q: std_logic;
+ signal i_cyc_o, i_stb_o, i_we_o: std_logic;
+ signal i_waitn: std_logic;
+begin
+ ctrl: process is
+ begin
+ wait until clk_i'EVENT and clk_i = '1';
+ if (rst_i = '1') then
+ i_cyc_o <= '0';
+ i_stb_o <= '0';
+ i_we_o <= '0';
+ else
+ if (a_cen = '0') then
+ i_stb_o <= not (a_rdn and a_wrn);
+ i_we_o <= not a_wrn;
+ i_cyc_o <= '1';
+ else
+ i_cyc_o <= '0';
+ i_stb_o <= '0';
+ i_we_o <= '0';
+ end if;
+ end if;
+ end process;
+ s_cyc_o <= i_cyc_o and not i_waitn;
+ s_stb_o <= i_stb_o and not i_waitn;
+ s_we_o <= i_we_o and not i_waitn;
+
+ w_ff1: d_ff port map (
+ d => s_ack_i,
+ clk => clk_i,
+ ena => '1',
+ clr => rst_i,
+ pre => '0',
+ q => wg_q
+ );
+
+ wg_clk <= not a_cen;
+ wg_pre <= wg_q or rst_i;
+ w_ff2: d_ff port map (
+ d => '0',
+ clk => wg_clk,
+ ena => '1',
+ clr => '0',
+ pre => wg_pre,
+ q => i_waitn
+ );
+ a_waitn <= i_waitn;
+
+ s_adr_o <= a_addr;
+ negate: for i in s_sel_o'RANGE generate s_sel_o(i) <= not a_byen(i); end generate;
+ s_dat_o <= a_data;
+
+ a_data_out: process is
+ begin
+ wait on s_dat_i, a_rdn, a_cen;
+ if (a_rdn = '0' and a_cen = '0') then
+ a_data <= s_dat_i;
+ else
+ a_data <= (others => 'Z');
+ end if;
+ end process;
+end wb_async_master;
+
+-------------------------------------------------------------------------------
+--
+-- wb_async_slave
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library work;
+use work.technology.all;
+
+entity wb_async_slave is
+ generic (
+ width: positive := 16;
+ addr_width: positive := 20
+ );
+ port (
+ clk_i: in std_logic;
+ rst_i: in std_logic := '0';
+
+ -- interface for wait-state generator state-machine
+ wait_state: in std_logic_vector (3 downto 0);
+
+ -- interface to wishbone master device
+ adr_i: in std_logic_vector (addr_width-1 downto 0);
+ sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
+ dat_i: in std_logic_vector (width-1 downto 0);
+ dat_o: out std_logic_vector (width-1 downto 0);
+ dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
+ we_i: in std_logic;
+ stb_i: in std_logic;
+ ack_o: out std_logic := '0';
+ ack_oi: in std_logic := '-';
+
+ -- interface to async slave
+ a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
+ a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
+ a_rdn: out std_logic := '1';
+ a_wrn: out std_logic := '1';
+ a_cen: out std_logic := '1';
+ -- byte-enable signals
+ a_byen: out std_logic_vector ((width/8)-1 downto 0)
+ );
+end wb_async_slave;
+
+architecture wb_async_slave of wb_async_slave is
+ -- multiplexed access signals to memory
+ signal i_ack: std_logic;
+ signal sm_ack: std_logic;
+
+ type states is (sm_idle, sm_wait, sm_deact);
+ signal state: states;
+ signal cnt: std_logic_vector(3 downto 0);
+begin
+ ack_o <= (stb_i and i_ack) or (not stb_i and ack_oi);
+ dat_o_gen: for i in dat_o'RANGE generate
+ dat_o(i) <= (stb_i and a_data(i)) or (not stb_i and dat_oi(i));
+ end generate;
+
+ -- For 0WS operation i_ack is an async signal otherwise it's a sync one.
+ i_ack_gen: process is
+ begin
+ wait on sm_ack, stb_i, wait_state, state;
+ if (wait_state = "0000") then
+ case (state) is
+ when sm_deact => i_ack <= '0';
+ when others => i_ack <= stb_i;
+ end case;
+ else
+ i_ack <= sm_ack;
+ end if;
+ end process;
+
+ -- SRAM signal-handler process
+ sram_signals: process is
+ begin
+ wait on state,we_i,a_data,adr_i,rst_i, stb_i, sel_i, dat_i;
+ if (rst_i = '1') then
+ a_wrn <= '1';
+ a_rdn <= '1';
+ a_cen <= '1';
+ a_addr <= (others => '-');
+ a_data <= (others => 'Z');
+ a_byen <= (others => '1');
+ else
+ case (state) is
+ when sm_deact =>
+ a_wrn <= '1';
+ a_rdn <= '1';
+ a_cen <= '1';
+ a_addr <= (others => '-');
+ a_data <= (others => 'Z');
+ a_byen <= (others => '1');
+ when others =>
+ a_addr <= adr_i;
+ a_rdn <= not (not we_i and stb_i);
+ a_wrn <= not (we_i and stb_i);
+ a_cen <= not stb_i;
+ a_byen <= not sel_i;
+ if (we_i = '1') then
+ a_data <= dat_i;
+ else
+ a_data <= (others => 'Z');
+ end if;
+ end case;
+ end if;
+ end process;
+
+ -- Aysnc access state-machine.
+ async_sm: process is
+-- variable cnt: std_logic_vector(3 downto 0) := "0000";
+-- variable state: states := init;
+ begin
+ wait until clk_i'EVENT and clk_i = '1';
+ if (rst_i = '1') then
+ state <= sm_idle;
+ cnt <= ((0) => '1', others => '0');
+ sm_ack <= '0';
+ else
+ case (state) is
+ when sm_idle =>
+ -- Check if anyone needs access to the memory.
+ -- it's rdy signal will already be pulled low, so we only have to start the access
+ if (stb_i = '1') then
+ case wait_state is
+ when "0000" =>
+ sm_ack <= '1';
+ state <= sm_deact;
+ when "0001" =>
+ sm_ack <= '1';
+ cnt <= "0001";
+ state <= sm_wait;
+ when others =>
+ sm_ack <= '0';
+ cnt <= "0001";
+ state <= sm_wait;
+ end case;
+ end if;
+ when sm_wait =>
+ if (cnt = wait_state) then
+ -- wait cycle completed.
+ state <= sm_deact;
+ sm_ack <= '0';
+ cnt <= "0000";
+ else
+ if (add_one(cnt) = wait_state) then
+ sm_ack <= '1';
+ else
+ sm_ack <= '0';
+ end if;
+ cnt <= add_one(cnt);
+ end if;
+ when sm_deact =>
+ if (stb_i = '1') then
+ case wait_state is
+ when "0000" =>
+ cnt <= "0000";
+ sm_ack <= '0';
+ state <= sm_wait;
+ when others =>
+ sm_ack <= '0';
+ cnt <= "0000";
+ state <= sm_wait;
+ end case;
+ else
+ sm_ack <= '0';
+ state <= sm_idle;
+ end if;
+ end case;
+ end if;
+ end process;
+end wb_async_slave;
+
+-------------------------------------------------------------------------------
+--
+-- wb_arbiter
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library work;
+use work.technology.all;
+
+entity wb_arbiter is
+ port (
+-- clk: in std_logic;
+ rst_i: in std_logic := '0';
+
+ -- interface to master device a
+ a_we_i: in std_logic;
+ a_stb_i: in std_logic;
+ a_cyc_i: in std_logic;
+ a_ack_o: out std_logic;
+ a_ack_oi: in std_logic := '-';
+ a_err_o: out std_logic;
+ a_err_oi: in std_logic := '-';
+ a_rty_o: out std_logic;
+ a_rty_oi: in std_logic := '-';
+
+ -- interface to master device b
+ b_we_i: in std_logic;
+ b_stb_i: in std_logic;
+ b_cyc_i: in std_logic;
+ b_ack_o: out std_logic;
+ b_ack_oi: in std_logic := '-';
+ b_err_o: out std_logic;
+ b_err_oi: in std_logic := '-';
+ b_rty_o: out std_logic;
+ b_rty_oi: in std_logic := '-';
+
+ -- interface to shared devices
+ s_we_o: out std_logic;
+ s_stb_o: out std_logic;
+ s_cyc_o: out std_logic;
+ s_ack_i: in std_logic;
+ s_err_i: in std_logic := '-';
+ s_rty_i: in std_logic := '-';
+
+ mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
+
+ -- misc control lines
+ priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
+ );
+end wb_arbiter;
+
+-- This acthitecture is a clean asyncron state-machine. However it cannot be mapped to FPGA architecture
+architecture behaviour of wb_arbiter is
+ type states is (idle,aa,ba);
+ signal i_mux_signal: std_logic;
+
+ signal e_state: states;
+begin
+ mux_signal <= i_mux_signal;
+
+ sm: process is
+ variable state: states;
+ begin
+ wait on a_cyc_i, b_cyc_i, priority, rst_i;
+ if (rst_i = '1') then
+ state := idle;
+ i_mux_signal <= priority;
+ else
+ case (state) is
+ when idle =>
+ if (a_cyc_i = '1' and (priority = '0' or b_cyc_i = '0')) then
+ state := aa;
+ i_mux_signal <= '0';
+ elsif (b_cyc_i = '1' and (priority = '1' or a_cyc_i = '0')) then
+ state := ba;
+ i_mux_signal <= '1';
+ else
+ i_mux_signal <= priority;
+ end if;
+ when aa =>
+ if (a_cyc_i = '0') then
+ if (b_cyc_i = '1') then
+ state := ba;
+ i_mux_signal <= '1';
+ else
+ state := idle;
+ i_mux_signal <= priority;
+ end if;
+ else
+ i_mux_signal <= '0';
+ end if;
+ when ba =>
+ if (b_cyc_i = '0') then
+ if (a_cyc_i = '1') then
+ state := aa;
+ i_mux_signal <= '0';
+ else
+ state := idle;
+ i_mux_signal <= priority;
+ end if;
+ else
+ i_mux_signal <= '1';
+ end if;
+ end case;
+ end if;
+ e_state <= state;
+ end process;
+
+ signal_mux: process is
+ begin
+ wait on a_we_i, a_stb_i, a_ack_oi, a_err_oi, a_rty_oi, a_cyc_i,
+ b_we_i, b_stb_i, b_ack_oi, b_err_oi, b_rty_oi, b_cyc_i,
+ s_ack_i, s_err_i, s_rty_i, i_mux_signal;
+ if (i_mux_signal = '0') then
+ s_we_o <= a_we_i;
+ s_stb_o <= a_stb_i;
+ s_cyc_o <= a_cyc_i;
+ a_ack_o <= (a_stb_i and s_ack_i) or (not a_stb_i and a_ack_oi);
+ a_err_o <= (a_stb_i and s_err_i) or (not a_stb_i and a_err_oi);
+ a_rty_o <= (a_stb_i and s_rty_i) or (not a_stb_i and a_rty_oi);
+ b_ack_o <= (b_stb_i and '0') or (not b_stb_i and b_ack_oi);
+ b_err_o <= (b_stb_i and '0') or (not b_stb_i and b_err_oi);
+ b_rty_o <= (b_stb_i and '0') or (not b_stb_i and b_rty_oi);
+ else
+ s_we_o <= b_we_i;
+ s_stb_o <= b_stb_i;
+ s_cyc_o <= b_cyc_i;
+ b_ack_o <= (b_stb_i and s_ack_i) or (not b_stb_i and b_ack_oi);
+ b_err_o <= (b_stb_i and s_err_i) or (not b_stb_i and b_err_oi);
+ b_rty_o <= (b_stb_i and s_rty_i) or (not b_stb_i and b_rty_oi);
+ a_ack_o <= (a_stb_i and '0') or (not a_stb_i and a_ack_oi);
+ a_err_o <= (a_stb_i and '0') or (not a_stb_i and a_err_oi);
+ a_rty_o <= (a_stb_i and '0') or (not a_stb_i and a_rty_oi);
+ end if;
+ end process;
+end behaviour;
+
+-- This acthitecture is a more-or-less structural implementation. Fits for FPGA realization.
+architecture FPGA of wb_arbiter is
+ component d_ff
+ port ( d : in STD_LOGIC;
+ clk: in STD_LOGIC;
+ ena: in STD_LOGIC := '1';
+ clr: in STD_LOGIC := '0';
+ pre: in STD_LOGIC := '0';
+ q : out STD_LOGIC
+ );
+ end component;
+
+ signal i_mux_signal: std_logic;
+
+ type states is (idle,aa,ba,XX);
+ signal e_state: states;
+
+ -- signals for a DFF in FPGA
+ signal idle_s, aa_s, ba_s: std_logic;
+
+ signal aa_clk, aa_ena, aa_clr, aa_pre: std_logic;
+ signal ba_clk, ba_ena, ba_clr, ba_pre: std_logic;
+
+begin
+ mux_signal <= i_mux_signal;
+
+ idle_s <= not (a_cyc_i or b_cyc_i);
+
+ aa_clr <= rst_i or not a_cyc_i;
+ aa_clk <= a_cyc_i;
+ aa_ena <= not b_cyc_i and priority;
+ aa_pre <= (a_cyc_i and not priority and not ba_s) or (a_cyc_i and not b_cyc_i);
+ aa_ff: d_ff port map (
+ d => '1',
+ clk => aa_clk,
+ ena => aa_ena,
+ clr => aa_clr,
+ pre => aa_pre,
+ q => aa_s
+ );
+
+ ba_clr <= rst_i or not b_cyc_i;
+ ba_clk <= b_cyc_i;
+ ba_ena <= not a_cyc_i and not priority;
+ ba_pre <= (b_cyc_i and priority and not aa_s) or (b_cyc_i and not a_cyc_i);
+ ba_ff: d_ff port map (
+ d => '1',
+ clk => ba_clk,
+ ena => ba_ena,
+ clr => ba_clr,
+ pre => ba_pre,
+ q => ba_s
+ );
+
+ i_mux_signal <= (priority and idle_s) or ba_s;
+
+ signal_mux: process is
+ begin
+ wait on a_we_i, a_stb_i, a_ack_oi, a_err_oi, a_rty_oi, a_cyc_i,
+ b_we_i, b_stb_i, b_ack_oi, b_err_oi, b_rty_oi, b_cyc_i,
+ s_ack_i, s_err_i, s_rty_i, i_mux_signal;
+ if (i_mux_signal = '0') then
+ s_we_o <= a_we_i;
+ s_stb_o <= a_stb_i;
+ s_cyc_o <= a_cyc_i;
+ a_ack_o <= (a_stb_i and s_ack_i) or (not a_stb_i and a_ack_oi);
+ a_err_o <= (a_stb_i and s_err_i) or (not a_stb_i and a_err_oi);
+ a_rty_o <= (a_stb_i and s_rty_i) or (not a_stb_i and a_rty_oi);
+ b_ack_o <= (b_stb_i and '0') or (not b_stb_i and b_ack_oi);
+ b_err_o <= (b_stb_i and '0') or (not b_stb_i and b_err_oi);
+ b_rty_o <= (b_stb_i and '0') or (not b_stb_i and b_rty_oi);
+ else
+ s_we_o <= b_we_i;
+ s_stb_o <= b_stb_i;
+ s_cyc_o <= b_cyc_i;
+ b_ack_o <= (b_stb_i and s_ack_i) or (not b_stb_i and b_ack_oi);
+ b_err_o <= (b_stb_i and s_err_i) or (not b_stb_i and b_err_oi);
+ b_rty_o <= (b_stb_i and s_rty_i) or (not b_stb_i and b_rty_oi);
+ a_ack_o <= (a_stb_i and '0') or (not a_stb_i and a_ack_oi);
+ a_err_o <= (a_stb_i and '0') or (not a_stb_i and a_err_oi);
+ a_rty_o <= (a_stb_i and '0') or (not a_stb_i and a_rty_oi);
+ end if;
+ end process;
+
+ gen_e_state: process is
+ begin
+ wait on idle_s,aa_s,ba_s;
+ if (idle_s = '1' and ba_s = '0' and aa_s = '0') then e_state <= idle;
+ elsif (idle_s = '0' and ba_s = '1' and aa_s = '0') then e_state <= aa;
+ elsif (idle_s = '0' and ba_s = '0' and aa_s = '1') then e_state <= ba;
+ else e_state <= XX;
+ end if;
+ end process;
+end FPGA;
+
+-------------------------------------------------------------------------------
+--
+-- wb_out_reg
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library work;
+use work.technology.all;
+
+entity wb_out_reg is
+ generic (
+ width : positive := 8;
+ bus_width: positive := 8;
+ offset: integer := 0
+ );
+ port (
+ clk_i: in std_logic;
+ rst_i: in std_logic;
+ rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
+
+ dat_i: in std_logic_vector (bus_width-1 downto 0);
+ dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
+ dat_o: out std_logic_vector (bus_width-1 downto 0);
+ q: out std_logic_vector (width-1 downto 0);
+ we_i: in std_logic;
+ stb_i: in std_logic;
+ ack_o: out std_logic;
+ ack_oi: in std_logic := '-'
+ );
+end wb_out_reg;
+
+architecture wb_out_reg of wb_out_reg is
+ signal content : std_logic_vector (width-1 downto 0);
+begin
+ -- output bus handling with logic
+ gen_dat_o: process is
+ variable rd_sel: std_logic;
+ begin
+ wait on dat_oi, we_i, stb_i, content;
+ rd_sel := stb_i and not we_i;
+ for i in bus_width-1 downto 0 loop
+ if (i >= offset and i < offset+width) then
+ dat_o(i) <= (dat_oi(i) and not rd_sel) or (content(i-offset) and rd_sel);
+ else
+ dat_o(i) <= dat_oi(i);
+ end if;
+ end loop;
+ end process;
+
+ -- this item never generates any wait-states
+ ack_o <= stb_i or ack_oi;
+
+ reg: process is
+ begin
+ wait until clk_i'EVENT and clk_i='1';
+ if (rst_i = '1') then
+ content <= rst_val;
+ else
+ if (stb_i = '1' and we_i = '1') then
+ content <= dat_i(width+offset-1 downto offset);
+ end if;
+ end if;
+ end process;
+ q <= content;
+end wb_out_reg;
Index: wb_vga/tags/a01/hv_sync.vhd
===================================================================
--- wb_vga/tags/a01/hv_sync.vhd (nonexistent)
+++ wb_vga/tags/a01/hv_sync.vhd (revision 8)
@@ -0,0 +1,149 @@
+--
+-- Horizontal and vertical sync generator.
+--
+-- (c) Copyright Andras Tantos 2001/03/31
+-- This code is distributed under the terms and conditions of the GNU General Public Lince.
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity hv_sync is
+ port (
+ clk: in std_logic;
+ pix_clk_en: in std_logic := '1';
+ reset: in std_logic := '0';
+
+ hbs: in std_logic_vector(7 downto 0);
+ hss: in std_logic_vector(7 downto 0);
+ hse: in std_logic_vector(7 downto 0);
+ htotal: in std_logic_vector(7 downto 0);
+ vbs: in std_logic_vector(7 downto 0);
+ vss: in std_logic_vector(7 downto 0);
+ vse: in std_logic_vector(7 downto 0);
+ vtotal: in std_logic_vector(7 downto 0);
+
+ h_sync: out std_logic;
+ h_blank: out std_logic;
+ v_sync: out std_logic;
+ v_blank: out std_logic;
+ h_tc: out std_logic;
+ v_tc: out std_logic;
+ blank: out std_logic
+ );
+end hv_sync;
+
+architecture hv_sync of hv_sync is
+ component sync_gen
+ port (
+ clk: in std_logic;
+ clk_en: in std_logic;
+ reset: in std_logic := '0';
+
+ bs: in std_logic_vector(7 downto 0);
+ ss: in std_logic_vector(7 downto 0);
+ se: in std_logic_vector(7 downto 0);
+ total: in std_logic_vector(7 downto 0);
+
+ sync: out std_logic;
+ blank: out std_logic;
+ tc: out std_logic;
+
+ count: out std_logic_vector (7 downto 0)
+ );
+ end component;
+ signal h_blank_i: std_logic;
+ signal v_blank_i: std_logic;
+ signal h_tc_i: std_logic;
+ signal hcen: std_logic;
+ signal vcen: std_logic;
+
+ constant h_pre_div_factor: integer := 3;
+ constant v_pre_div_factor: integer := 3;
+ subtype h_div_var is integer range 0 to h_pre_div_factor;
+ subtype v_div_var is integer range 0 to v_pre_div_factor;
+
+begin
+
+ h_pre_div : process is
+ variable cntr: h_div_var;
+ begin
+ wait until clk'EVENT and clk='1';
+ if (reset = '1') then
+ cntr := 0;
+ hcen <= '0';
+ else
+ if (pix_clk_en='1') then
+ if (cntr = h_pre_div_factor) then
+ cntr := 0;
+ hcen <= '1';
+ else
+ cntr := cntr+1;
+ hcen <= '0';
+ end if;
+ else
+ hcen <= '0';
+ end if;
+ end if;
+ end process;
+
+ h_sync_gen : sync_gen
+ port map (
+ clk => clk,
+ clk_en => hcen,
+ reset => reset,
+
+ bs => hbs,
+ ss => hss,
+ se => hse,
+ total => htotal,
+
+ sync => h_sync,
+ blank => h_blank_i,
+ tc => h_tc_i
+ );
+
+ h_tc <= h_tc_i;
+
+ v_pre_div : process is
+ variable cntr: v_div_var;
+ begin
+ wait until clk'EVENT and clk='1';
+ if (reset = '1') then
+ cntr := 0;
+ vcen <= '0';
+ else
+ if (h_tc_i='1') then
+ if (cntr = v_pre_div_factor) then
+ cntr := 0;
+ vcen <= '1';
+ else
+ cntr := cntr+1;
+ vcen <= '0';
+ end if;
+ else
+ vcen <= '0';
+ end if;
+ end if;
+ end process;
+
+ v_sync_gen : sync_gen
+ port map (
+ clk => clk,
+ clk_en => vcen,
+ reset => reset,
+
+ bs => vbs,
+ ss => vss,
+ se => vse,
+ total => vtotal,
+
+ sync => v_sync,
+ blank => v_blank_i,
+ tc => v_tc
+ );
+
+ blank <= h_blank_i or v_blank_i;
+ h_blank <= h_blank_i;
+ v_blank <= v_blank_i;
+end hv_sync;
Index: wb_vga/tags/a01/technology.vhd
===================================================================
--- wb_vga/tags/a01/technology.vhd (nonexistent)
+++ wb_vga/tags/a01/technology.vhd (revision 8)
@@ -0,0 +1,194 @@
+--
+-- Technology mapping library. ALTERA edition.
+--
+-- (c) Copyright Andras Tantos 2001/03/31
+-- This code is distributed under the terms and conditions of the GNU General Public Lince.
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library exemplar;
+use exemplar.exemplar_1164.all;
+
+package technology is
+ function add_one(inp : std_logic_vector) return std_logic_vector;
+ function is_zero(inp : std_logic_vector) return boolean;
+ function sl(l: std_logic_vector; r: integer) return std_logic_vector;
+-- procedure inc(data : inout std_logic_vector);
+ function "+"(op_l, op_r: std_logic_vector) return std_logic_vector;
+
+ component d_ff is
+ port ( d : in STD_LOGIC;
+ clk: in STD_LOGIC;
+ ena: in STD_LOGIC := '1';
+ clr: in STD_LOGIC := '0';
+ pre: in STD_LOGIC := '0';
+ q : out STD_LOGIC
+ );
+ end component;
+ component fifo is
+ generic (fifo_width : positive;
+ used_width : positive;
+ fifo_depth : positive
+ );
+ port (d_in : in std_logic_vector(fifo_width-1 downto 0);
+ clk : in std_logic;
+ wr : in std_logic;
+ rd : in std_logic;
+ a_clr : in std_logic := '0';
+ s_clr : in std_logic := '0';
+ d_out : out std_logic_vector(fifo_width-1 downto 0);
+ used : out std_logic_vector(used_width-1 downto 0);
+ full : out std_logic;
+ empty : out std_logic
+ );
+ end component;
+end technology;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library exemplar;
+use exemplar.exemplar_1164.all;
+
+package body technology is
+ function "+"(op_l, op_r: std_logic_vector) return std_logic_vector is
+ begin
+ return exemplar_1164."+"(op_l, op_r);
+ end;
+
+ function add_one(inp : std_logic_vector) return std_logic_vector is
+ variable one: std_logic_vector(inp'RANGE) := (others => '0');
+ begin
+ one(0) := '1';
+ return exemplar_1164."+"(inp,one);
+ end;
+
+ function is_zero(inp : std_logic_vector) return boolean is
+ variable zero: std_logic_vector(inp'RANGE) := (others => '0');
+ begin
+ return (inp = zero);
+ end;
+
+ function sl(l: std_logic_vector; r: integer) return std_logic_vector is
+ begin
+ return exemplar_1164.sl(l,r);
+ end;
+-- procedure inc(data : inout std_logic_vector) is
+-- begin
+-- data := addone(data);
+-- end;
+end package body technology;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library exemplar;
+use exemplar.exemplar_1164.all;
+
+library lpm;
+use lpm.all;
+
+entity fifo is
+ generic (fifo_width : positive;
+ used_width : positive;
+ fifo_depth : positive
+ );
+ port (d_in : in std_logic_vector(fifo_width-1 downto 0);
+ clk : in std_logic;
+ wr : in std_logic;
+ rd : in std_logic;
+ a_clr : in std_logic := '0';
+ s_clr : in std_logic := '0';
+ d_out : out std_logic_vector(fifo_width-1 downto 0);
+ used : out std_logic_vector(used_width-1 downto 0);
+ full : out std_logic;
+ empty : out std_logic
+ );
+end fifo;
+
+architecture altera of fifo is
+ component lpm_fifo
+ generic (LPM_WIDTH : positive;
+ LPM_WIDTHU : positive;
+ LPM_NUMWORDS : positive;
+ LPM_SHOWAHEAD : string := "OFF";
+ LPM_TYPE : string := "LPM_FIFO";
+ LPM_HINT : string := "UNUSED");
+ port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
+ CLOCK : in std_logic;
+ WRREQ : in std_logic;
+ RDREQ : in std_logic;
+ ACLR : in std_logic;
+ SCLR : in std_logic;
+ Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
+ USEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);
+ FULL : out std_logic;
+ EMPTY : out std_logic);
+ end component;
+begin
+ altera_fifo: lpm_fifo
+ generic map (
+ LPM_WIDTH => fifo_width,
+ LPM_WIDTHU => used_width,
+ LPM_NUMWORDS => fifo_depth,
+ LPM_SHOWAHEAD => "OFF",
+ LPM_TYPE => "LPM_FIFO",
+ LPM_HINT => "UNUSED"
+ )
+ port map (
+ DATA => d_in,
+ CLOCK => clk,
+ WRREQ => wr,
+ RDREQ => rd,
+ ACLR => a_clr,
+ SCLR => s_clr,
+ Q => d_out,
+ USEDW => used,
+ FULL => full,
+ EMPTY => empty
+ );
+end altera;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library altera_exemplar;
+use altera_exemplar.all;
+
+entity d_ff is
+ port ( d : in STD_LOGIC;
+ clk: in STD_LOGIC;
+ ena: in STD_LOGIC := '1';
+ clr: in STD_LOGIC := '0';
+ pre: in STD_LOGIC := '0';
+ q : out STD_LOGIC
+ );
+end d_ff;
+
+architecture altera of d_ff is
+ component dffe
+ port ( D : in STD_LOGIC;
+ CLK: in STD_LOGIC;
+ ENA: in STD_LOGIC;
+ CLRN: in STD_LOGIC;
+ PRN: in STD_LOGIC;
+ Q : out STD_LOGIC);
+ end component;
+ signal clrn,prn: std_logic;
+begin
+ clrn <= not clr;
+ prn <= not pre;
+ ff: dffe port map (
+ D => d,
+ CLK => clk,
+ ENA => ena,
+ CLRN => clrn,
+ PRN => prn,
+ Q => q
+ );
+end altera;
+
+-- Sythetizer library. Contains STD_LOGIC arithmetics
+
Index: wb_vga/tags/a01/video_engine.vhd
===================================================================
--- wb_vga/tags/a01/video_engine.vhd (nonexistent)
+++ wb_vga/tags/a01/video_engine.vhd (revision 8)
@@ -0,0 +1,223 @@
+--
+-- File: video_engine.vhd
+--
+-- (c) Copyright Andras Tantos 2001/03/31
+-- This code is distributed under the terms and conditions of the GNU General Public Lince.
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library work;
+use work.technology.all;
+
+entity video_engine is
+ generic (
+ v_mem_width: positive := 16;
+ v_addr_width: positive:= 20;
+ fifo_size: positive := 256;
+ dual_scan_fifo_size: positive := 256
+ );
+ port (
+ clk: in std_logic;
+ clk_en: in std_logic := '1';
+ reset: in std_logic := '0';
+
+ total: in std_logic_vector(v_addr_width-1 downto 0); -- total video memory size in bytes 7..0
+ fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold
+ bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8
+ multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans
+
+ hbs: in std_logic_vector(7 downto 0);
+ hss: in std_logic_vector(7 downto 0);
+ hse: in std_logic_vector(7 downto 0);
+ htotal: in std_logic_vector(7 downto 0);
+ vbs: in std_logic_vector(7 downto 0);
+ vss: in std_logic_vector(7 downto 0);
+ vse: in std_logic_vector(7 downto 0);
+ vtotal: in std_logic_vector(7 downto 0);
+
+ pps: in std_logic_vector(7 downto 0);
+
+ high_prior: out std_logic; -- signals to the memory arbitrer to give high
+ -- priority to the video engine
+ v_mem_rd: out std_logic; -- video memory read request
+ v_mem_rdy: in std_logic; -- video memory data ready
+ v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address
+ v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data
+
+ h_sync: out std_logic;
+ h_blank: out std_logic;
+ v_sync: out std_logic;
+ v_blank: out std_logic;
+ h_tc: out std_logic;
+ v_tc: out std_logic;
+ blank: out std_logic;
+ video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
+ );
+end video_engine;
+
+architecture video_engine of video_engine is
+ component hv_sync
+ port (
+ clk: in std_logic;
+ pix_clk_en: in std_logic := '1';
+ reset: in std_logic := '0';
+
+ hbs: in std_logic_vector(7 downto 0);
+ hss: in std_logic_vector(7 downto 0);
+ hse: in std_logic_vector(7 downto 0);
+ htotal: in std_logic_vector(7 downto 0);
+ vbs: in std_logic_vector(7 downto 0);
+ vss: in std_logic_vector(7 downto 0);
+ vse: in std_logic_vector(7 downto 0);
+ vtotal: in std_logic_vector(7 downto 0);
+
+ h_sync: out std_logic;
+ h_blank: out std_logic;
+ v_sync: out std_logic;
+ v_blank: out std_logic;
+ h_tc: out std_logic;
+ v_tc: out std_logic;
+ blank: out std_logic
+ );
+ end component;
+
+ component mem_reader
+ generic (
+ v_mem_width: positive := 16;
+ v_addr_width: positive:= 20;
+ fifo_size: positive := 256;
+ dual_scan_fifo_size: positive := 256
+ );
+ port (
+ clk: in std_logic;
+ clk_en: in std_logic;
+ pix_clk_en: in std_logic;
+ reset: in std_logic := '0';
+
+ total: in std_logic_vector(v_addr_width-1 downto 0); -- total video memory size in bytes 7..0
+ fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold
+ bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8
+ multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans
+
+ high_prior: out std_logic; -- signals to the memory arbitrer to give high
+ -- priority to the video engine
+ v_mem_rd: out std_logic; -- video memory read request
+ v_mem_rdy: in std_logic; -- video memory data ready
+ v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address
+ v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data
+
+ blank: in std_logic; -- video sync generator blank output
+ h_tc: in std_logic; -- horizontal sync pulse. Must be 1 clock wide!
+ video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
+ );
+ end component;
+
+ signal pix_clk_en: std_logic;
+
+ signal i_h_sync: std_logic;
+ signal i_h_blank: std_logic;
+ signal i_v_sync: std_logic;
+ signal i_v_blank: std_logic;
+ signal i_h_tc: std_logic;
+ signal i_v_tc: std_logic;
+ signal i_blank: std_logic;
+
+begin
+ pps_gen: process is
+ variable cnt: std_logic_vector(3 downto 0);
+ begin
+ wait until clk'EVENT and clk = '1';
+ if (reset = '1') then
+ cnt := (others => '0');
+ pix_clk_en <= '0';
+ else
+ if (clk_en = '0') then
+ pix_clk_en <= '0';
+ else
+ if (cnt = pps(3 downto 0)) then
+ cnt := (others => '0');
+ pix_clk_en <= '1';
+ else
+ cnt := add_one(cnt);
+ pix_clk_en <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ mem_engine : mem_reader
+ generic map (
+ v_mem_width => v_mem_width,
+ v_addr_width => v_addr_width,
+ fifo_size => fifo_size,
+ dual_scan_fifo_size => dual_scan_fifo_size
+ )
+ port map (
+ clk => clk,
+ clk_en => clk_en,
+ pix_clk_en => pix_clk_en,
+ reset => reset,
+ total => total,
+ fifo_treshold => fifo_treshold,
+ bpp => bpp,
+ multi_scan => multi_scan,
+ high_prior => high_prior,
+ v_mem_rd => v_mem_rd,
+ v_mem_rdy => v_mem_rdy,
+ v_mem_addr => v_mem_addr,
+ v_mem_data => v_mem_data,
+ blank => i_blank,
+ h_tc => i_h_tc,
+ video_out => video_out
+ );
+
+ sync_engine : hv_sync
+ port map (
+ clk => clk,
+ pix_clk_en => pix_clk_en,
+ reset => reset,
+
+ hbs => hbs,
+ hss => hss,
+ hse => hse,
+ htotal => htotal,
+ vbs => vbs,
+ vss => vss,
+ vse => vse,
+ vtotal => vtotal,
+
+ h_sync => i_h_sync,
+ h_blank => i_h_blank,
+ v_sync => i_v_sync,
+ v_blank => i_v_blank,
+ h_tc => i_h_tc,
+ v_tc => i_v_tc,
+ blank => i_blank
+ );
+
+ -- Delay all sync signals with one pixel. That's becouse of the syncron output of the mem_reader
+ sync_delay: process is
+ begin
+ wait until (clk'EVENT and clk='1');
+ if (reset = '1') then
+ h_sync <= '0';
+ h_blank <= '1';
+ v_sync <= '0';
+ v_blank <= '1';
+ blank <= '1';
+ elsif (pix_clk_en = '1') then
+ h_sync <= i_h_sync;
+ h_blank <= i_h_blank;
+ v_sync <= i_v_sync;
+ v_blank <= i_v_blank;
+ blank <= i_blank;
+ end if;
+ end process;
+
+ h_tc <= i_h_tc;
+ v_tc <= i_v_tc;
+
+end video_engine;
+
Index: wb_vga/tags
===================================================================
--- wb_vga/tags (nonexistent)
+++ wb_vga/tags (revision 8)
wb_vga/tags
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##